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1、relationship, established equivalent relationship 14, and subject: application problem (4)-scores and percentage application problem review content overview answers scores, and percentage application problem of key is: according to meaning, (1) determine standard volume (units 1) (2) find associate
2、volume rate corresponds to relationship, Then in-line solution. Category fraction multiplication word problem score Division applications engineering problem problem XV, a subject: review of the measurement of the amount of capacity, measurement and units of measurement of common units of measuremen
3、t and their significance in rate 1, currency, length, area, volume, unit size, volume, weight and rate. (Omitted) 2, commonly used time units and their relationships. (Slightly) with a measurement units Zhijian of of poly 1, and of method 2, and poly method 3, and of method and poly method of relati
4、onship measurement distance of method 1, and tool measurement 2, and estimates 16, and subject: geometry preliminary knowledge (1)-line and angle review content line, and segment, and Ray, and vertical, and parallel, and angle angle of classification (slightly) 17, and subject: geometry preliminary
5、knowledge (2)-plane graphics review content triangle, and edges shaped, and round, and fan axisymmetric graphics perimeter and area combination graphics of area subject : Preliminary knowledge (3)-review of solid content category 1-d shapes are divided into: cylinder and cone 2, column is divided in
6、to: cuboid, square 3, cone cone of the features of cuboids and cubes relationship between characteristics of circular cone is slightly solid surface area and volume 1, size 2, table .和EDA实验实验报告EDA实验报告基于FPGA技术实现62256 Sram芯片的读写控制及校验器的Quartus II程序设计指导教师： 学号姓名： 实验小组成员： 一、实验目的及程序设计性能要求：如右图所示，为62256芯片关键图，
7、管脚功能介绍如下：A0 A14地址总线(Address) D0 /D7输入/输出口(Input/output) CS端口选择(Chip select) WE输入始能(Write enable) OE输出始能(Output enable) VCC电源始能(Power supply) VSS接地(Ground)性能要求：进行芯片进行工作室，CS，OE端口应置低电平。进行写操作时，WE端口信号应为负脉冲，进行读操作时WE端口应置高电平。所需设计的控制校验功能如下：正确输出62256芯片所需的使能端信号。在进行校验工作时，正确的控制读写控制端口WE的电平状态，并顺利输入与输出地址信号及数据信号，并进行
8、实时校验。校验的具体要求是，共分为两步：第一，向62256芯片中输入地址与数据信号，其中奇数地址输入55，偶数地址输入AA。直到向所有内存（32KB）中写入数据后，进行读操作。此时将读入的数据与芯片内实时运算的，内存中应该有的数值进行比较，若值相同则输出为1，否则输出为0。第二步基本与第一步相同，只需改变奇地址输入为AA，偶地址输入为55。二、程序设计部分1.设计方案框图：数据时钟信号校验结果控制地址SRAM62256存储器校验电路复位控制2.程序状态转移图：Addr=2fh/DoutAddr2fhAddr2fh3.程序流程图：初始化检验步数Quan=0YNNNwr 负脉冲addr=addr+
9、1奇地址data_reg=55偶地址data_reg=AAwr=1addr=addr+1奇地址data_reg=55偶地址data_reg2fhaddr2fhdata=data_reg验证正确dout=1验证错误dout=0结束YYYNNNwr 负脉冲addr=addr+1奇地址data_reg=AA偶地址data_reg=55wr=1addr=addr+1奇地址data_reg=AA偶地址data_reg2fhaddr2fhdata=data_reg验证正确dout=1验证错误dout=0结束YYYN4Verilog HDL程序源代码：module wyw(clk, addr , wr, c
10、e, oe, data, dout,areset,data_reg, realaddr);inout7:0 data;input areset;input clk;outputwr,oe,ce;output14:0 addr;output dout;output 7:0 data_reg;reg14:0addr;output14:0 realaddr;reg14:0realaddr;wire7:0 data;wirece=0;wire oe=0;reg wr;reg dout;parameter Idle=3h0, Write_begin=3h1, Write_end =3h2, Read_b
11、egin =3h3, Read_end =3h4;reg qiuyu;reg quan;reg2:0 STATE;reg7:0 data_reg;/程序输入输出端口及状态定义assign data=wr?data_reg:8hzz;/定义双向数据端口data的值always (posedge areset or posedge clk )/时钟上升沿激励及异步复位beginif (areset) /异步复位设置begin wr=1b0;data_reg=8h00;addr=15b0;dout=1b0;STATE=Idle;end elsebegin case(STATE)/非复位情况下程序运行
12、，状态判断Idle: /第一状态Idle的定义begin wr=1; addr=15b0; realaddr=15b0; data_reg=8h00; STATE=Write_begin; dout=1b0; qiuyu=1b0; quan=quan;/校验步数设定，1,2循环 end Write_begin:/第二状态Write_begin的定义 begin addr=addr+15h1; /地址自加一realaddr=addr-15h1; /由于波形显示时直接显示地址自加一结果，因此加入一个真实地址的显示 wr=wr;/We输出负脉冲的设定if (quan)/校验步数判断，并输入不同数据beginqiuyu=addr%2;/奇偶地址判断，并存入不同数据if(qiuyu)begindata_reg=8h55;endelse begindata_reg=8h0AA; end STATE=Write_end;endelsebeginqiuyu=addr%2;if(qiuyu)begindata_reg=8h0AA;endelse begindata_reg=8h55; end STATE=Write_end; end
