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1、REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or oth
2、erwise under any patent or patent rights of Analog Devices. a ADF4106 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329- Fax: 781/326-8703 Analog Devices, Inc., 2001 PLL Frequency Synthesizer FEATURES 6.0 GHz Bandwidth 2.7 V to 3.3 V Power Supply Separate Charge Pump Sup
3、ply (VP) Allows Extended Tuning Voltage in 3 V Systems Programmable Dual Modulus Prescaler 8/9, 16/17, 32/33, 64/65 Programmable Charge Pump Currents Programmable Anti-Backlash Pulsewidth 3-Wire Serial Interface Analog and Digital Lock Detect Hardware and Software Power-Down Mode APPLICATIONS Broadb
4、and Wireless Access Instrumentation Wireless LANS Base Stations For Wireless Radio FUNCTIONAL BLOCK DIAGRAM 14-BIT R COUNTER R COUNTER LATCH FUNCTION LATCH AB COUNTER LATCH 24-BIT INPUT REGISTER 22 14 REFIN CLK DATA LE AVDDDVDD PHASE FREQUENCY DETECTOR CHARGE PUMP REFERENCE VP CPGNDRSET CURRENT SETT
5、ING 2 CURRENT SETTING 1 CPI3 CPI2 CPI1CPI6 CPI5 CPI4 LOCK DETECT CP MUXOUT AVDD SDOUT HIGH Z 19 13-BIT B COUNTER PRESCALER P/P + 1 RFINA RFINB 6-BIT A COUNTER FROM FUNCTION LATCH LOAD LOAD M3 M2 M1 MUX 6 N = BP + A CE AGNDDGND ADF4106 13 GENERAL DESCRIPTION The ADF4106 frequency synthesizer can be u
6、sed to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters and a dual-modulus
7、prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) c
8、an be implemented if the synthe- sizer is used with an external loop filter and VCO (Voltage Controlled Oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high-frequency systems, simplifying system architecture and lowering cost. REV. 02 ADF4106SPECIFICATION
9、S1 BChips2 ParameterB Version1(typ)UnitTest Conditions/Comments RF CHARACTERISTICSSee Figure 3 for Input Circuit RF Input Frequency (RFIN)30.5/6.00.5/6.0GHz min/max RF Input Sensitivity10/010/0dBm min/max Maximum Allowable Prescaler Output Frequency4300300MHz max REFIN CHARACTERISTICS REFIN Input Fr
10、equency20/25020/250MHz min/maxFor f 20 MHz, Use DC-Coupled Square Wave, (0 to VDD) REFIN Input Sensitivity50.8/AVDD0.8/AVDDV p-p min/maxAC-Coupled; When DC-Coupled, 0 to VDD max (CMOS Compatible) REFIN Input Capacitance1010pF max REFIN Input Current100100A max PHASE DETECTOR Phase Detector Frequency
11、65656MHz max CHARGE PUMP ICP Sink/SourceProgrammable, See Table V High Value55mA typWith RSET = 5.1 k Low Value625625A typ Absolute Accuracy2.52.5% typWith RSET = 5.1 k RSET Range2.7/102.7/10k typSee Table V ICP Three-State Leakage Current11nA typ Sink and Source Current Matching22% typ0.5 V ? VCP ?
12、 VP 0.5 V ICP vs. VCP1.51.5% typ0.5 V ? VCP ? VP 0.5 V ICP vs. Temperature22% typVCP = VP/2 LOGIC INPUTS VINH, Input High Voltage1.41.4V min VINL, Input Low Voltage0.60.6V max IINH/IINL, Input Current11A max CIN, Input Capacitance1010pF max LOGIC OUTPUTS VOH, Output High Voltage1.41.4V minOpen Drain
13、 Output Chosen 1 k Pull-up to 1.8 V VOH, Output High Voltage1.41.4V minCMOS Output Chosen IOH100100A max VOL, Output Low Voltage0.40.4V maxIOL = 500 A POWER SUPPLIES AVDD2.7/3.32.7/3.3V min/V max DVDDAVDDAVDD VPAVDD/5.5AVDD/5.5V min/V maxAVDD ? VP ? 5.5 V IDD7 (AIDD + DIDD)1513mA max13 mA typ IP0.40
14、.4mA maxTA = 25C Power-Down Mode8 (AIDD + DIDD)1010A typ (AVDD = DVDD = 3 V ? 10%; AVDD VP 5.5 V; AGND = DGND = CPGND = 0 V; RSET = 5.1 k?; dBm referred to 50 ?; TA = TMIN to TMAX unless otherwise noted.) 3REV. 0 BChips2 ParameterB Version1(typ)UnitTest Conditions/Comments NOISE CHARACTERISTICS ADF4
15、106 Phase Noise Floor9174174dBc/Hz typ 25 kHz PFD Frequency 166166dBc/Hz typ 200 kHz PFD Frequency 159159dBc/Hz typ 1 MHz PFD Frequency Phase Noise Performance10 VCO Output 900 MHz Output119393dBc/Hz typ 1 kHz Offset and 200 kHz PFD Frequency 5800 MHz Output127474dBc/Hz typ 1 kHz Offset and 200 kHz
16、PFD Frequency 5800 MHz Output138484dBc/Hz typ 1 kHz Offset and 1 MHz PFD Frequency Spurious Signals 900 MHz Output1190/9290/92dBc typ 200 kHz/400 kHz and 200 kHz PFD Frequency 5800 MHz Output1265/7065/70dBc typ 200 kHz/400 kHz and 200 kHz PFD Frequency 5800 MHz Output1370/7570/75dBc typ 1 MHz/2 MHz and 1 MHz PFD Frequency NOTES 1Operating temperature range (B Version) is 40C to +85C. 2The BChip specifications a
