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1、Hiroshi Iwai Frontier Research Center Tokyo Institute of Technology CSTIC 2013 Keynote Talk 1 Future of Nano CMOS Future of Nano CMOS TechnologyTechnology Kerry Hotel, Shanghai, China, March 17, 2013 1. Back ground for nano-electronics 1900 “Electronics” started. Device: Vacuum tube Device feature s
2、ize: 10 cm 1970 “Micro-Electronics” started. Device: Si MOS integrated circuits Device feature size: 10 m Major Appl.: Amplifier (Radio, TV, Wireless etc.) Major Appl.: Digital (Computer, PC, etc.) ?Technology Revolution ?Technology Revolution 2000 “Nano-Electronics” started. Device: Still, Si CMOS
3、integrated circuits Device feature size: 100 nm Major Appl.: Digital (-processor, cell phone, etc.) ?Technology Revolution? Maybe, just evolution or innovation! But very important so many innovations! Now, 2013 “Nano-Electronics” continued. Device: Still, Si CMOS integrated circuits Device feature s
4、ize: near 10 nm Major Appl.: Still Digital (-processor, cell phone, etc.) But, so many important emerging applications for smart society. Still evolution and innovation Future, “Nano-Electronics” still continued? Device: Still, Si CMOS integrated circuits? Device feature size: ? nm, what is the limi
5、t? Application: New application? ?Any Technology Revolution? Questions for future What is special or new for Nano-Electronics? In 1990s, people expected completely new mechanism or operational principle due the nano size, like quantum mechanical effects. However, no fancy new operational principle w
6、as found. At least for logic application, there is no success story for “Beyond CMOS devices” to replace Si-CMOS. Of course, I do not deny the importance of Beyond CMOS technology development. It is becoming very important as CMOS approach its limit. L Diffusive transport 4000/900cm2/Vs was gained i
7、n a single channel material Incontent of 2040% improves perfomance Z. Yuan et al., pp.185, VLSI2012 (Stanford Uni) InGaSb as channel material (stanford) Electron MobilityHole Mobility AlGaSb creates barrier for both electrons and holes Si Si InGaSb InGaSb Metal S/D and InAs buffer layer are used as
8、performance boosters. DIBL=84 mV/V and SS=105 mV/V was shown for Lch= 55 nm when Incontent was higher. S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni) Metal S/D InGaAs MOSFET (Tokyo Uni) SS: nMOS: 90 (mV/decade) pMOS: 190 (mV/decade) Si2H6plasma passivation is employed which creates Si layer at inter
9、face. Common gate stack (gate metal and dielectric) were used for both p and ntype High intrinsic peak GM,Sat=of 465 S/m at VDS=-1.1 V was achieved for LG=250 nm. X. Gong, et al. (National Uni of Singapore), VLSI2012, p.99. Common InGaAsGeSn gate stack (NUS) LG= 5m VGS-VTH= 02.0V InGaAs nanowire tra
10、nsistor(Hokkaido Uni)InGaAs nanowire transistor(Hokkaido Uni) T. Fukui, et al. (Hokkaido Univ), IEDM2011, p.773. Core-multishell InGaAs nanowires grown without buffer layer on Si substrate (bottom up approach) At Vd= 1 V peak transconductance of 500 mS/mm is achieved (roughly x3 InGaAs nanowire) Tri
11、Tri- -gate InGaAs QWgate InGaAs QW- -FET(Intel)FET(Intel) M. Radosavljevic, et al.(Intel), IEDM2011, p.765. Steepest SS and smallest DIBL ever reported (Wfin = 30nm) Tri-gate structure has superiority electrostatic controllability compared to ultra-thin body planar structure Gate all around InGaAs M
12、OSFET(Purdue)Gate all around InGaAs MOSFET(Purdue) P. D. Ye, et al (Purdue Univ)., IEDM2011, p.769. DIBL was suppressed down to Lch = 50nm and Gm,max=701mS/mm at Vds= 1V Inversion mode In0.53Ga0.47As MOSFET with ALD Al2O3/WN with well electrostatic properties Wfin= 50nm Wfin= 30nm DIBL =135 mV/V and
13、 drive current over 840 A/ m at Lch = 130nm and Vds= 1.5V was achieved H.C. Chin, et al. (National Uni of Singapore)., EDL2011,Vol.32 p.146. LCH= 130nm InGaAs FinFET (NSU)InGaAs FinFET (NSU) GeGe- -nanowire pMOSFET (AIST,Tsukuba)nanowire pMOSFET (AIST,Tsukuba) Using Ni-Ge alloy as metal S/D Signific
14、antly reduces contact resistance K. Ikeda, et al. (AIST, Tsukuba), VLSI2012, p.165. High saturation current and high mobility eff= 855 cm2/Vs at Ns =5x1012cm-2 and saturation drain current of 731A/m at Vd = -1V Lg= 65nm Wwire= 20nm VD= -1V VD= -0.5V VD= -0.05V Vg-Vth= -2V S-H. Hsu, et al. (NNDL,Taiw
15、an), IEDM2011, p. 825. Selective etching of high defect Ge near Ge/Si interface is used which improves gate controllability. ION/IOFF= 105and SS= 130 mV/dec And ION= 235 m/ m at VD= -1V Ge triangular pMOSFET (NNDL,Taiwan)Ge triangular pMOSFET (NNDL,Taiwan) Ge Triangular Ge Rectangular Lg2WfinLg 105
16、135 Year Power per MOSFET (P) PLg3 (Scaling) EOT Limit 0.70.8 nm EOT=0.5nm Today EOT=1.0nm Now 45nm node One order of Magnitude Si HfO2 Metal SiO2/SiON Si High-k Metal Direct Contact Of high-k and Si Si Metal SiO2/SiON 0.50.7nm Introduction of High-k Still SiO2 or SiON Is used at Si interface For the past 45 years SiO2 and SiON For gate insulator EOT can be reduced further beyond 0.5 nm by using direct contact to Si By choosing appropriate materials and p
