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1、Course Review,Logic and Computer Design Fundamentals,Wang Dong-hui Jan. 2011,Outline,About Final Exam Highlights & Exercises,ABOUT FINAL EXAM,Course Review,Final Exam,Fill in the blank (20 points, 2pt/per) Multiple Choice (20 points, 2pt/per) Optimization (12 points, 6pt/per) Circuit Analysis (18 p
2、oints) Combinational circuit Sequential circuit Logic Design (30 points) Combinational circuit Sequential circuit,HIGHLIGHTS & EXERCISES,Course Review,Chapter 1,Conversion between number systems Binary number, hexadecimal number Eg. ( 1101 1111)2 = (DF)16Conversion between binary number and decimal
3、code BCD (binary-coded decimal) Eg. (1001 0101)BCD - ( 0101 1111)2 - (5F)16 Parity Bit 100 0001 - 0100 0001 (with even parity) - 1100 0001 (with odd parity) How to generate odd parity bit P for any 5-bit binary number D4D3D2D1D0？ Gray Code & ASCII Character Code,Chapter 2,Boolean algebra Dual of an
4、algebraic expression: ORAND, 0s 1s DeMorgans theorem: (X + Y) = X Y and (XY) = X + Y Identities of Boolean algebra: X+YZ=(X+Y)(X+Z) Consensus theorem: XY+XZ+YZ = XY+XZ, (X+Y)(X+Z)(Y+Z)=(X+Y)(X+Z) Complement of a function Standard forms Product terms, sum terms, SOP, POS Minterms, Maxterms, SOM, POM
5、Relationship between SOP and SOM? SOM and POM? Two-level circuit optimization Karnaugh map (K-map), Prime implicants, essential prime implicants Simplifying in SOP form (with dont care conditions) Cost criteria: gate input cost,Chapter 2,Other gates Buffer, NAND, NOR, 3-state buffer (Hi-Z), XOR, XNO
6、R Exclusive-OR operator and gates Identities of XOR operation: XY = XY =(XY) X(YZ) = (XY)Z = (XY Z) Odd function and even function Use odd function to generate even parity bit Use even function to generate odd parity bit The even function is obtained by replacing the output gate with an XNOR gate. P
7、odd=XYZ, Peven= Podd=(XYZ) High-impedance outputs 3-state buffer (Hi-Z) Transmission gates,Chapter 2,Exercises: The dual of an algebraic expression is obtained by 1) interchanging OR and AND operations and 2) replacing 1s by 0s and 0s by 1s. Use DeMorgans Theorem to complement a function: 1) Interch
8、ange AND and OR operators 2).Complement each constant value and literal Four variables odd function has _ “1” squares in its corresponding K-Map. A. 4 B. 7 C. 8 D. 14 The gate input cost G of function is _. A. 15 B. 14 C. 13 D. 12 Which of the following logical gates can be used as a controllable in
9、verter? _. A. AND gate B. XOR gate C. Buffer gate D. OR gate The Essential Prime Implicants in the K-Map given below are _. A. YZ, XZ B. XY, XY C. XY, XZ D. YZ, XY Given below are the waveforms of input A, B and output F of a logic device. Then the device is a _ gate. A. NAND B. NOR C. XOR D. OR,Cha
10、pter 2,Exercises: According to the following logic circuit diagram, write down the corresponding Boolean function and optimize it to the form of SOP,Chapter 3,Design procedure: specification, formulation, optimization, technology mapping, verification Technology parameters: fan-in, fan-out, noise ma
11、rgin, cost, propagation delay, power dissipation How to calculate gate delay based on fan-out? p.101, example 3-1 Seven-segment display How to design a BCD-to-Seven-Segment decoder? p.107, example 3-3 Technology mapping How to implement a Boolean function with NAND gates?How to implement a Boolean f
12、unction with a small cell library?,Chapter 3,Delay Model: Transport delay, Inertial delay, rejection time Programmable implementation technologies ROM, PROM, PAL,Chapter 3,Programmable implementation technologies PLA,Chapter 4,n-to-m-Line Decoder: n m 2n 3-to-8-Line decoder Demultiplexer: Decoder wi
13、th Enable m-to-n-Line Encoder: n m 2n Multiplexers control inputs (Sn - 1, S0) called selection inputs 2-to-1-Line Multiplexer Combinational Function Implementation Decoders and OR gates, Multiplexers (and inverter) ROMs PLAs: doesnt provide full decoding of the variables, so it doesnt generate all
14、the minterms PALs: similar to the PLAs Lookup Tables,Chapter 4,Combinational Function Implementation Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2n-line decoder, and m OR gates (one for each output) a ROM with n-bit addresses and m-bit data output Implement
15、m functions of n variables with an m-wide 2n-to-1-line multiplexer Implement m functions of n+1 variables with an m-wide 2n-to-1-line multiplexer and a single inverter Can any combinational circuit with n inputs and m outputs be implemented with a PLA with n inputs and m outputs ? a PAL with n input
16、s and m outputs ?,Chapter 4,Exercise Problem 4-23. Implement a binary full adder with a dual 4-to-1-line multiplexer and a single inverter.,Chapter 5,Half Adder Full Adder carry generate: XY carry propagate: XY Binary Ripple Carry Adder Carry Lookahead Adder Binary subtraction Signed 2s Complement subtraction 1100 - 0011 = 1001 0011 - 1100 = 0111 Signed-Complement Arithmetic Binary adder-subtractors,
