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1、集成电路设计报告Spi_slave 模块设计姓名:曹奥班级：无 26/微 21学号：2012011140 1目录Project 要求2设计电路5设计代码9功能仿真15DC 综合 .15Encounter 布线18文件清单18总结19附录:spi_slave_post.v input clk, rst_n, spi_clk, spi_cs, spi_mosi;input 7:0state_indication;output spi_miso;wire flag_write;wire spi_cs;wire 4:0count;wire 3:0address;wire 7:0data_in_tmp_
2、reg, data_out_tmp_reg;wire spi_cs_posedge_valid,spi_cs_negedge_valid,spi_clk_posedge_valid,spi_clk_negedge_valid;findedge 10f1(spi_cs,rst_n,clk,spi_clk,spi_cs_posedge_valid,spi_cs_negedge_valid,spi_clk_posedge_valid,spi_clk_negedge_valid);counter c1(count,spi_clk,rst_n,spi_cs,clk,flag_write,spi_cs_p
3、osedge_valid,spi_clk_posedge_valid);register r1(clk,rst_n,address,data_in_tmp_reg,data_out_tmp_reg,flag_write,count);controller c2(address,flag_write,count,clk, rst_n, spi_clk, spi_cs, spi_mosi,state_indication,spi_miso,data_in_tmp_reg, data_out_tmp_reg,spi_clk_posedge_valid,spi_clk_negedge_valid);e
4、ndmodulemodule counter(count,spi_clk,rst_n,spi_cs,clk,flag_write,spi_cs_posedge_valid,spi_clk_posedge_valid);output reg 4:0count;input spi_clk,rst_n,spi_cs,clk,flag_write,spi_cs_posedge_valid,spi_clk_posedge_valid;always(posedge clk)beginif(rst_n)begin11count6.感谢一下老师助教的帮助，不然 encounter 没法做了附录:spi_sla
5、ve_post.v input spi_cs, rst_n, clk, spi_clk;output spi_cs_posedge_valid, spi_cs_negedge_valid, spi_clk_posedge_valid,spi_clk_negedge_valid;wire n1, n2;wire 1:0 temp_cs;wire 1:0 temp_clk;20DFFRHQX1 temp_cs_reg0 ( .D(spi_cs), .CK(clk), .RN(rst_n), .Q(temp_cs0);DFFRHQX1 temp_cs_reg1 ( .D(temp_cs0), .CK
6、(clk), .RN(rst_n), .Q(temp_cs1) );DFFRHQX1 temp_clk_reg0 ( .D(spi_clk), .CK(clk), .RN(rst_n), .Q(temp_clk0) );DFFRHQX1 temp_clk_reg1 ( .D(temp_clk0), .CK(clk), .RN(rst_n), .Q(temp_clk1) );AND2X1 U3 ( .A(n1), .B(temp_cs1), .Y(spi_cs_negedge_valid) );NOR2X1 U4 ( .A(temp_clk1), .B(n2), .Y(spi_clk_posed
7、ge_valid) );NOR2X1 U5 ( .A(temp_cs1), .B(n1), .Y(spi_cs_posedge_valid) );INVX2 U6 ( .A(temp_clk0), .Y(n2) );INVX2 U7 ( .A(temp_cs0), .Y(n1) );AND2X1 U8 ( .A(n2), .B(temp_clk1), .Y(spi_clk_negedge_valid) );endmodulemodule counter ( count, spi_clk, rst_n, spi_cs, clk, flag_write, spi_cs_posedge_valid,
8、 spi_clk_posedge_valid );output 4:0 count;input spi_clk, rst_n, spi_cs, clk, flag_write, spi_cs_posedge_valid,21spi_clk_posedge_valid;wire N3, N4, N5, N6, N7, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12,add_29_S2/carry4 , add_29_S2/carry3 , add_29_S2/carry2 ;DFFHQX1 count_reg4 ( .D(n8), .CK(cl
9、k), .Q(count4) );DFFHQX1 count_reg3 ( .D(n9), .CK(clk), .Q(count3) );DFFHQX1 count_reg2 ( .D(n10), .CK(clk), .Q(count2) );DFFHQX1 count_reg1 ( .D(n11), .CK(clk), .Q(count1) );DFFHQX1 count_reg0 ( .D(n12), .CK(clk), .Q(count0) );NOR3BX1 U3 ( .AN(rst_n), .B(spi_cs_posedge_valid), .C(n3), .Y(n1) );AND2
10、X1 U4 ( .A(spi_clk_posedge_valid), .B(rst_n), .Y(n3) );ADDHXL U5 ( .A(count1), .B(count0), .CO(add_29_S2/carry2 ), .S(N4) );ADDHXL U6 ( .A(count2), .B(add_29_S2/carry2 ), .CO(add_29_S2/carry3 ), .S(N5) );ADDHXL U7 ( .A(count3), .B(add_29_S2/carry3 ), .CO(add_29_S2/carry4 ), .S(N6) );OAI2BB1X1 U8 ( .
11、A0N(count4), .A1N(n1), .B0(n2), .Y(n8) );NAND2X1 U9 ( .A(N7), .B(n3), .Y(n2) );OAI2BB1X1 U10 ( .A0N(count3), .A1N(n1), .B0(n4), .Y(n9) );NAND2X1 U11 ( .A(N6), .B(n3), .Y(n4) );OAI2BB1X1 U12 ( .A0N(count2), .A1N(n1), .B0(n5), .Y(n10) );NAND2X1 U13 ( .A(N5), .B(n3), .Y(n5) );22OAI2BB1X1 U14 ( .A0N(cou
12、nt1), .A1N(n1), .B0(n6), .Y(n11) );NAND2X1 U15 ( .A(N4), .B(n3), .Y(n6) );OAI2BB1X1 U16 ( .A0N(count0), .A1N(n1), .B0(n7), .Y(n12) );NAND2X1 U17 ( .A(N3), .B(n3), .Y(n7) );INVX2 U18 ( .A(count0), .Y(N3) );XOR2X1 U19 ( .A(add_29_S2/carry4 ), .B(count4), .Y(N7) );endmodulemodule register ( clk, rst_n,
13、 address, data_in_tmp_reg, data_out_tmp_reg, flag_write, count );input 3:0 address;input 7:0 data_in_tmp_reg;output 7:0 data_out_tmp_reg;input 4:0 count;input clk, rst_n, flag_write;wire N9, N10, N11, N12, reg_map157 , reg_map156 ,reg_map155 , reg_map154 , reg_map153 ,reg_map152 , reg_map151 , reg_m
14、ap150 ,reg_map147 , reg_map146 , reg_map145 ,reg_map144 , reg_map143 , reg_map142 ,reg_map141 , reg_map140 , reg_map137 ,23reg_map136 , reg_map135 , reg_map134 ,reg_map133 , reg_map132 , reg_map131 ,reg_map130 , reg_map127 , reg_map126 ,reg_map125 , reg_map124 , reg_map123 ,reg_map122 , reg_map121 ,
15、 reg_map120 ,reg_map117 , reg_map116 , reg_map115 ,reg_map114 , reg_map113 , reg_map112 ,reg_map111 , reg_map110 , reg_map107 ,reg_map106 , reg_map105 , reg_map104 ,reg_map103 , reg_map102 , reg_map101 ,reg_map100 , reg_map97 , reg_map96 , reg_map95 ,reg_map94 , reg_map93 , reg_map92 , reg_map91 ,reg_map90 , reg_map87 , reg_map86 , reg_map85 ,r
