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1、,MIPI Protocol Introduction,MIPI Development Team 2010-9-2,What is MIPI?,MIPI stands for Mobile Industry Processor InterfaceMIPI Alliance is a collaboration of mobile industry leaders.Objective to promote open standards for interfaces to mobile application processors.Intends to speed deployment of n
2、ew services to mobile users by establishing Spec.Board Members in MIPI AllianceIntel, Motorola, Nokia, NXP,Samsung, ST, TI,What is MIPI?,MIPI Alliance Specification for displayDCS (Display Command Set)DCS is a standardized command set intended for command mode display modules.DBI, DPI (Display Bus I
3、nterface, Display Pixel Interface)DBI：Parallel interfaces to display modules having display controllers and frame buffers.DPI：Parallel interfaces to display modules without on-panel display controller or frame buffer.DSI, CSI (Display Serial Interface, Camera Serial Interface)DSI specifies a high-sp
4、eed serial interface between a host processor and display module.CSI specifies a high-speed serial interface between a host processor and camera module.D-PHYD-PHY provides the physical layer definition for DSI and CSI.,DSI Layers,DCS spec,DSI spec,D-PHY spec,Outline,D-PHY Introduction Lane Module, S
5、tate and Line levels Operating Modes Escape Mode System Power States Electrical Characteristics Summary,Introduction for D-PHY,D-PHY describes a source synchronous, high speed, low power, low cost PHY A PHY configuration contains A Clock Lane One or more Data Lanes Three main lane types Unidirection
6、al Clock Lane Unidirectional Data Lane Bi-directional Data Lane Transmission Mode Low-Power signaling mode for control purpose：10MHz (max) High-Speed signaling mode for fast-data traffic：80Mbps 1Gbps per Lane D-PHY low-level protocol specifies a minimum data unit of one byte A transmitter shall send
7、 data LSB first, MSB last. D-PHY suited for mobile applications DSI：Display Serial Interface A clock lane, One to four data lanes. CSI：Camera Serial Interface,Two Data Lane PHY Configuration,Lane Module,PHY consists of D-PHY (Lane Module) D-PHY may contain Low-Power Transmitter (LP-TX) Low-Power Rec
8、eiver (LP-RX) High-Speed Transmitter (HS-TX) High-Speed Receiver (HS-RX) Low-Power Contention Detector (LP-CD) Three main lane types Unidirectional Clock Lane Master：HS-TX, LP-TX Slave：HS-RX, LP-RX Unidirectional Data Lane Master：HS-TX, LP-TX Slave：HS-RX, LP-RX Bi-directional Data Lane Master, Slave
9、：HS-TX, HS-RX,LP-TX, LP-RX, LP-CD,Universal Lane Module Architecture,Lane States and Line Levels,The two LP-TXs drive the two Lines of a Lane independently and single-ended. Four possible Low-Power Lane states (LP-00, LP-01, LP-10, LP-11) A HS-TX drives the Lane differentially. Two possible High Spe
10、ed Lane states (HS-0, HS-1) During HS transmission the LP Receivers observe LP-00 on the Lines Line Levels (typical) LP：01.2V HS：100300mV (Swing：200mV) Lane States LP-00, LP-01, LP-10, LP-11 HS-0, HS-1,Operating Modes,There are three operating modes in Data Lane Escape mode, High-Speed (Burst) mode
11、and Control mode Possible events starting from the Stop State of control mode Escape mode request (LP-11LP-10LP-00LP-01LP-00) High-Speed mode request (LP-11LP-01LP-00) Turnaround request (LP-11LP-10LP-00LP-10LP-00),Escape Mode,Escape mode is a special operation for Data Lanes using LP states. With t
12、his mode some additional functionality becomes available：LPDT, ULPS, Trigger A Data Lane shall enter Escape mode via LP-11LP-10LP-00LP-01LP-00 Once Escape mode is entered, the transmitter shall send an 8-bit entry command to indicate the requested action. Escape mode uses Spaced-One-Hot Encoding. me
13、ans each Mark State is interleaved with a Space State (LP-00). Send Mark-0/1 followed by a Space to transmit a zero-bit/ one-bit A Data Lane shall exit Escape mode via LP-10LP-11 Ultra-Low Power State During this state, the Lines are in the Space state (LP-00) Exited by means of a Mark-1 state with
14、a length TWAKEUP(1ms) followed by a Stop state.,Escape Mode,Clock Lane Ultra-Low Power State,A Clock Lane shall enter ULPS via LP-11LP-10LP-00exited by means of a Mark-1 with a length TWAKEUP followed by a Stop State LP-10 TWAKEUP LP-11 The minimum value of TWAKEUP is 1ms,High-Speed Data Transmissio
15、n,The action of sending high-speed serial data is called HS transmission or burst.Start-of-Transmission LP-11LP-01LP-00SoT(0001_1101) HS Data Transmission Burst All Lanes will start synchronously But may end at different times The clock Lane shall be in High-Speed mode, providing a DDR Clock to the
16、Slave side End-of-Transmission H Toggles differential state immediately after last payload data bitand keeps that state for a time THS-TRAIL,High-Speed Clock Transmission,Switching the Clock Lane between Clock Transmission and LP Mode A Clock Lane is a unidirectional Lane from Master to Slave In HS mode, the clock Lane provides a low-swing, differential DDR clock signal. the Clock Burst always starts and ends with an HS-0 state. the Clock Burst always contains an even number of transitions,
