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1、The World Leader in High Performance Signal Processing SolutionsSAR型ADC串行读读取和设计设计 要点叶健Sept. 2013SAR型ADC的CONV信号2SAR型ADC的CONV信号3Reading after a conversion and reading during a conversion4Understand the timing specifications pre- condition5Understand the timing specifications pre- condition6e.g. Simple
2、 calculation of max sampling rate when reading after a conversion by SPI mode71)Assume no OS, Vdrive = 2.7V, 0.3Vdrive0.7Vdrive as logic input level 2)tconv = 4.15us (max) 3)t1 = 45ns (max); t2 = 25ns (min) 4)fsclk = 12.5MHz (min) = 8X16 clock = 10.24us 5)A total time of tcycle = 4.15us + 45ns + 25n
3、s + 10.24us = 14.45us 6)Take 0.05us as the design buffer = 15.5us 7)Fsample (max) = 64.5kspsQuestion8Datasheet 上的9.4us哪里来的，你刚刚才算下来明明是14. 5us么？！A real case: why my ADC value is only half?9MCUAD7606AD7606AD7606AD7606SCLKA real case: how to calculate the data delay after sclk from low to high?FPGA IP C
4、oreclock signal IO delayclock trace delayADC “t19”data trace delaydata IO delayT total delayWhen isolated, things getting more worse11FPGAISOLATIONSCLKSDOADUM1401tpd = 1 nstpd = 1 nst = 3 nst = 4 ns tpd = 45 nst = 49 ns t = 50 nsQtco = 11 nstpd = 1 ns tpd = 45 nstpd = 1 nst = 61 nst = 62 nst = 107 n
5、st = 108 nsOs cQ SCLKSDODtsu = 3 nst = 111 ns12ADUM1401710ns + (16 x 111ns)400KSPSADUM1401 with SCLK loopback (max rate thru iso = 45Mhz)710ns + (16 x 22ns) + 100ns860KSPSCustomer Isolation issue with AD7980 WorkaroundSCLKMMOSIMISOSCLKSMREG1MREG2SREGSPI MasterSPI SlaveSCLK LoopbackA real case by sin
6、gle ground ADCuCommon interfacing mode to PulSARs eg. AD7980 3 wire modeuContinuous SCLK operation on BF SPORT, (+ many processors)uSensitivity to activity on SCLK during sensitive bit trialslCMOS inputs, large signal swing and ground bouncelOnly 1 GND pin on these partslPerformance degradation 1dB
7、SNR with continuous SCLK at 16 bit leveluSimplest solution is to gate the SCLK externally with CSPerformance to 18 bits, Burst vs Continuous SCLKSPORT vs SPI BF527uSPORT lHardware interface low JitterlContinuous SCLKlDMA possiblelFaster SCLK rates 60MHzlAny number of SCLKs in frameuSPIlLimited HW CS
8、 implementations, when SW based interface - More jitter on CSlSCLK is framed with CSlSlower SCLK rates 30MHzlSCLKs are in multiples of 8Sampling Clock Jitter and Aperture Jitter Increase ADC NoiseSAMPLING CLOCKdV dtTOTAL JITTER = t j (RMS)TOTAL JITTER =(ADC APERTURE JITTER) 2 + (SAMPLING CLOCK JITTE
9、R) 2SWITCH DRIVERINPUT SIGNALINPUT SAMPLING CLOCKCHOLDSNR Due to Aperture and Sampling Clock Jittertj = 1pstj = 10pstj = 100pstj = 1nsSNR SNR = = 20log20log10101 1 2 2p pf ft tj jfin/HzSNR/dBClocking AD7626uStandard eval board CED1Z uses FPGA generated CNV inputlFPGAs do not specify jitter, SNR performance degrades as input tone is increaseduNew development on SDP-H using AD9513 to generate to CNV clockuAD7626 will be released on this new platformAD7626 SNR Performance, FPGA CNV Vs AD9513 CNV
