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1、Cadence Design Systems, Inc.Cadences Solution for High-Speed Design2confidentialAgendaWhat is High-Speed Design?Ideal High-Speed Design Process Introduction to SPECCTRAQuest Power Integrity SPECCTRAQuest Demonstration3confidentialThe Day of “High-Speed” Has Come “Pc-board designers, meanwhile, were
2、retooling in 1999 for high-speed design. Signal integrity, once confined to high-end boards, has become everybodys problem”Richard Goering, commenting on why the PCB layout market grew 20% while the IC layout market shrunk 30%, in EETimes 4/10/2000 page 704confidentialWelcome Networking!Hammerhead N
3、etworks5confidentialAgendaWhat is High-Speed Design?Ideal High-Speed Design Process SPECCTRAQuest Demonstration Introduction to SPECCTRAQuest Power Integrity NOW6confidentialWhat is “High-Speed” ?Over 50 MHz is “High-Speed”“High-Speed” isnt related to frequency, its a function of rise timesA net is
4、“High-Speed” when its round-trip delay is greater than twice its edge-speedA signal is “High-Speed” when it is faster than anything youve designed before“High-Speed” occurs when skin effect and dielectric loss effects become importantHuh?7confidentialQuestion: Which is a “High-Speed” Problem?8confid
5、entialAnswer: They BOTH Are !9confidentialDefinition of High-SpeedA net can be considered High-Speedwhen you have to do something other than simply connect it.10confidentialHigh-Speed Design Involves 2 Things Nets that are understood, and must be constrained Nets that must be analyzed to be understo
6、od, and then constrained11confidential Nets that are understood, and must be constrained Nets that must be analyzed to be understood, and then constrainedSDRAM DIMM LayoutMODELSDatasheets Front-side Bus Simulation12confidentialMost Tools Force You to ChooseGreat Simulator!AnalyzeConstrainGreat Layou
7、t System!Hmm.13confidentialBut for High-Speed You Need BOTHAll in ONEintegrated & interactive environment !Analyze & ConstrainLets Go!14confidential15confidentialSPECCTRAQuest: Integrated Constraint & AnalysisModel Development & VerificationTopology Entry & FloorplanningConstraint Driven LayoutAnaly
8、zeConstrainSPECCTRAQuest helps you manage the processof High-Speed PCB development through both Simulation Analysis & Constraint-Driven Layout tasksA Complete Solution!Pre-Route Soln-Space AnalysisPost Route Analysis VerificationVerification16confidentialExpanding Existing ProcessPhysical Model Crea
9、tionOutline/ Floorplan/ Room Def/Schematic Model CreationSchematic CreationSCHEMATICLAYOUTTo Final VerificationnetlistSI Clean RouteconstraintsBack- AnnotateRe-use Topology FilesTopology FilesTopology FilesDerive ConstraintsElectrical Model CreationHIGH-SPEEDyesnoPost-Route Analysisrules/ criticals/
10、 placement / ACsOK?“IP” LibraryPCB Routing17confidentialAgendaWhat is High-Speed Design?Ideal High-Speed Design Process SPECCTRAQuest Demonstration Introduction to SPECCTRAQuest Power Integrity NOW18confidentialIdeal High-Speed Design FlowModel Development & VerificationTopology Entry & Floorplannin
11、gConstraint Driven LayoutAnalyzeConstrainDevelopment Process FlowPre-Route Soln-Space AnalysisPost Route Analysis VerificationVerificationModel Development & Verification19confidentialNeed Flexible Device Modeling Language (DML)Todays models come in many styles and formats Cadence DML can model all
12、formats AND advanced behaviors (for example, Merced / Itanium) Quad ModelsVersion 2.1 Version 3.2IBISPackage, Transmission Line, Connector, Cable ModelsSPICE ModelsEBD ModelsCadence DMLcant do “M” element today20confidentialIdeal High-Speed Design FlowModel Development & VerificationTopology Entry &
13、 FloorplanningConstraint Driven LayoutAnalyzeConstrainDevelopment Process FlowPre-Route Soln-Space AnalysisPost Route Analysis VerificationVerificationPre-Route Soln-Space Analysis21confidentialPre-Route Solution Space Analysis Exhaustive “pre-layout” analysis of manufacturing and design variances U
14、sed to define topologies, routing rules and termination strategies Crosstalk and data pattern dependencies may be taken into consideration Swept-parameter analysis is used extensively to cover all combinations of conditions Need flexibility to define any kind of simulation and any kind of measuremen
15、t criteria22confidentialOutput of pre-layout process is an electronic constraint file that can be used to guide the layout processAnalyzeTopology TemplatesDerive and Save “Solution Space”Constrain23confidentialIdeal High-Speed Design FlowModel Development & VerificationTopology Entry & Floorplanning
16、Constraint Driven LayoutAnalyzeConstrainDevelopment Process FlowPre-Route Soln-Space AnalysisPost Route Analysis VerificationVerificationTopology Entry & Floorplanning24confidentialHigh-Speed PCB Design Now Requires Both Electronic Inputs to Floorplanning & Routing25confidentialTopology Entry and Floorplanning Design rules derived from solution space analysis guide the placem
