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1、Solid-State Drive(SSD) andSolid State Drive(SSD) and Memory System InnovationMemory System InnovationKen Takeuchi Dept. of Electrical Engineering and Information Systems University of Tokyo1Univ. of Tokyo - INRIA - Ecole des Mines Paris - INRETS Joint Symposium Ken TakeuchiDefinition of SSDSSD : Sol
2、id State Drive Mass storage to replace HDD of PC/automobile application.application. SSD consists of NAND Flash Memory and NAND tll(+RAM)controller(+RAM)J. Elliott, WinHEC 2007, SS-S499b_WH07. All car manufactures are interested in SSD2Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Sym
3、posium Ken TakeuchiAll car manufactures are interested in SSD.Reliability bottleneck for automobile applicationReliable DeviceReliable CircuitReliabilityReliabilityReliable OS/Computer architectureReliable OS/Computer architectureNeed collaboration with IT/SW communityKen TakeuchiUniv. of Tokyo - IN
4、RIA - Ecole des Mines Paris -INRETS Joint Symposium 3Need collaboration with IT/SW communityKey Challenge of SSDNeed to improve device reliability such as endurance, data retention, and disturb.endurance, data retention, and disturb. Ridif NANDd NANDtllRequire co-design of NAND and NAND controller c
5、ircuits to best optimize both NAND and NAND controllers.OS/Computer architecture innovation essential.4Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium Ken TakeuchiK. TakeuchiOutlineNAND OverviewO ee SSD Overview Operating System for SSD Green IT with SSD Summary5Univ. of Tokyo
6、 - INRIA - Ecole des Mines Paris -INRETS Joint Symposium Ken TakeuchiOutlineNAND OverviewO ee SSD Overview Operating System for SSD Green IT with SSD Summary6Univ. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium Ken TakeuchiNAND Flash MemoryK Kanda ISSCC 200843nm 16Gb NANDNAND flash
7、Memory cell : K. Kanda, ISSCC, 2008.NAND flash memory chipMemory circuity Floating Gate-FETKen TakeuchiUniv. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium 7Page & Block of NAND Flash MemoryPage : program/read unitBlock : Erase unitBitlineBitlineBitline2 S ltt2 S ltt Source-line2 S
8、elect-gate 32 Word-lines2 Select-gate 32 Word-linesMemory cells are sandwiched by select gates. Contactless structure : ideal 4F2cell sizeKen TakeuchiUniv. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium Contactless structure : ideal 4F cell sizeF.Masuoka, IEDM 1987, pp.552-555.Top
9、View of NAND Flash Cell ArraySource-line (first metal)Bitline (second metal)STIActive areaSGDSGDSGSSGS Word-linesContact to bitlineContact to source-lineSimple structure : High scalability, High yieldKen TakeuchiUniv. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium K. Imamiya, ISSCC
10、 1999, pp.112-113.MLC vs. SLCSLC : Single-level cell or 1bit/cell MLCM lti llll2bit/llMLC : Multi-level cell or 2bit/cell2bit/cell : Long production record since 2001 3bit/cell or 4bit/cell : Will be commercialized this year. Existing SSD uses SLC but MLC based SSD will g be commercialized this year
11、.MLC (Multi-level cell)SLC (Single-level cell)“0”“1”“2”“3”Number of memory cells “0”“1”Number of memory cellsVthVthKen TakeuchiUniv. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium VthNAND Density Trend10010B/mm21sity MB55% growth / year 1y dens0.1Memory0.01M199419961998200020022004
12、2006YearMLC (Multi-level cell) NAND flashISSCC paperKen TakeuchiUniv. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium 11SLC (Single-level cell) NAND flash()K. Takeuchi, ISSCC 2006,pp.144-145.NAND Program Speed Trend12MLC (Multi-level cell) NAND flashISSCC paper810MB/secSLC (Single-l
13、evel cell) NAND flashf5M-pixel 5photos/secFTTH68peed MHDTV 60fps4gram sp4M-pixel 3photos/sec2ProgMPEG2 VGA 30fpsMotion JPEG VGA 30fps01994199619982000200220042006MPEG2 VGA 30fpsYearMLC performance is comparable with SLCKen TakeuchiUniv. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposiu
14、m 12MLC performance is comparable with SLC.K. Takeuchi, ISSCC 2006,pp.144-145.Chip Architecture56nm 8Gbit NAND Flash MemoryKen TakeuchiUniv. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium 13K. Takeuchi, ISSCC 2006,pp.144-145.NAND Operation PrincipleReadBit-line (0.8V?0V)“0”“1”Numbe
15、r of memory cellsSelected word-lineVread (4.5V)Bit line (0.8V?0V)Vth01Bit line voltageSelected word-line (Read voltage : 0V) Read voltageBit-line voltage“1”Vread (4.5V)Time“0” Vread (4.5V)0V?After precharging, bit-lines are discharged through the memory cell.? Ult dllbid tthltVd? Unselected cells are biased to the pass voltage, Vread.? Small cell read current (1uA) ? Slow random access (50us)Ken TakeuchiUniv. of Tokyo - INRIA - Ecole des Mines Paris -INRETS Joint Symposium 14? Serial access : 30-50ns ? Fast read = 20-30MB/secNAND Operation Principle (Cont)Program : Electron injection18V0V0V18
