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1、*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intels T
2、erms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. April 1994COPYRIGHTINTEL CORPORATION, 1995Order Number: 270946-0058XC196
3、MC INDUSTRIAL MOTOR CONTROL MICROCONTROLLER 87C196MC 16 Kbytes of On-Chip OTPROM* 87C196MC, ROM 16 Kbytes of On-Chip Factory-Programmed OTPROM 80C196MC ROMlessYHigh-Performance CHMOS 16-Bit CPUY16 Kbytes of On-Chip OTPROM/ Factory-Programmed OTPROMY488 bytes of On-Chip Register RAMYRegister to Regis
4、ter ArchitectureYUp to 53 I/O LinesYPeripheral Transaction Server (PTS) with 11 Prioritized SourcesYEvent Processor Array (EPA) 4 High Speed Capture/Compare Modules 4 High Speed Compare ModulesYExtended Temperature StandardYTwo 16-Bit Timers with Quadrature Decoder InputY3-Phase Complementary Wavefo
5、rm GeneratorY13 Channel 8/10-Bit A/D with Sample/ Hold with Zero Offset Adjustment H/WY14 Prioritized Interrupt SourcesYFlexible 8-/16-Bit External BusY1.75 ms 16 x 16 MultiplyY3 ms 32/16 DivideYIdle and Power Down ModesThe 8XC196MC is a 16-bit microcontroller designed primarily to control 3 phase A
6、C induction and DC brush- less motors. The 8XC196MC is based on Intels MCS?96 16-bit microcontroller architecture and is manufac- tured with Intels CHMOS process.The 8XC196MC has a three phase waveform generator specifically designed for use in Inverter motor control applications. This peripheral al
7、lows for pulse width modulation, three phase sine wave generation with minimal CPU intervention. It generates 3 complementary non-overlapping PWM pulses with resolutions of 0.125 ms (edge trigger) or 0.250 ms (centered).The 8XC196MC has 16 Kbytes on-chip OTPROM/ROM and 488 bytes of on-chip RAM. It i
8、s available in three packages; PLCC (84-L), SDIP (64-L) and EIAJ/QFP (80-L).Note that the 64-L SDIP package does not include P1.4, P2.7, P5.1 and the CLKOUT pins.Operational characteristics are guaranteed over the temperature range ofb40C toa85C.The 87C196MC contains 16 Kbytes on-chip OTPROM. The 83
9、C196MC contains 16 Kbytes on-chip ROM. All references to the 80C196MC also refers to the 83C196MC and 87C196MC unless noted.*OTPROM (One Time Programmable Read Only Memory) is the same as EPROM but it comes in an unwindowed package and cannot be erased. It is user programmable.8XC196MC2709461NOTE: C
10、onnections between the standard I/O ports and the bus are not shown.Figure 1. 87C196MC Block Diagram28XC196MCPROCESS INFORMATIONThis device is manufactured on PX29.5, a CHMOS III-E process. Additional process and reliability infor- mation is available in the Intel Quality System Handbook.27094616EXA
11、MPLE: N87C196MC is 84-Lead PLCC OTPROM, 16 MHz. For complete package dimensional data, refer to the Intel Packaging Handbook (Order Number 240800).NOTE: 1. EPROMs are available as One Time Programmable (OTPROM) only.Figure 3. The 8XC196MC Family NomenclatureThermal CharacteristicsPackageijaijcTypePL
12、CC35C/W13C/WQFP56C/W12C/WSDIPTBDTBDAll thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operation conditions and application. See the IntelPackaging Handbook(order number 240800) for a description of Intels thermal impedance
13、test methodology.8XC196MC Memory MapDescriptionAddressExternal Memory or I/O0FFFFH 06000HInternal ROM/EPROM or External5FFFH Memory (Determined by EA)2080HReserved. Must contain FFH.207FH (Note 5)205EHPTS Vectors205DH 2040HUpper Interrupt Vectors203FH 2030HROM/EPROM Security Key202FH 2020HReserved.
14、Must contain FFH.201FH (Note 5)201CHReserved. Must Contain 20H201BH (Note 5)CCB1201AHReserved. Must Contain 20H2019H (Note 5)CCB02018HReserved. Must contain FFH.2017H (Note 5)2014HLower Interrupt Vectors2013H 2000HSFRs1FFFH 1F00HExternal Memory1EFFH 0200H488 Bytes Register RAM (Note 1)01FFH 0018HCPU
15、 SFRs (Notes 1, 3)0017H 0000HNOTES: 1. Code executed in locations 0000H to 03FFH will be forced external. 2. Reserved memory locations must contain 0FFH unless noted. 3. Reserved SFR bit locations must contain 0. 4. Refer to 8XC196KC for SFR descriptions. 5. WARNING: Reserved memory locations must n
16、ot be written or read. The contents and/or function of these lo- cations may change with future revisions of the device. Therefore, a program that relies on one or more of these locations may not function properly.38XC196MC2709462NOTE: *The pin sequence is correct. The 64-Lead SDIP package does not include the following pins: P1.4/ACH12, P2.7/COMPARE3, P5.1/INST, CLKOUT.Figure 2. 64-Lead Shrink DIP (SDIP) Package48XC196MC2709463NOTE: NC means No Connect. Do not connect
