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1、1applied research laboratoryapplied research laboratoryDavid E. TaylorUsers Guide: Fast IP Lookup (FIPL) in the FPXGigabit Kits Workshop 1/2002applied research laboratoryapplied research laboratoryDavid E. TaylorFIPL System Design Each FIPL Engine performs a longest matching prefix lookup on a singl
2、e 32-bit IPv4 destination address FIPL Engine Controller scales to required lookup throughput with minimal hardware resource usage Instantiate required number of parallel lookup engines 4 engines in current configuration (2.4 Gb/s link) Pipeline memory accessesPacket I/OPPSwitch FabricPhysical Links
3、CPTIPPTITIFIPL EngineFIPL Engine ControllerFIPL EngineFIPL WrapperProcessorControlSRAM InterfacePacket I/O FIPL Wrapper Buffers packets Supports up to 4 virtual ports Control Processor Handles data structure updates2applied research laboratoryapplied research laboratoryDavid E. TaylorDesign Overview
4、SRAM1SRAM2IP Lookup EnginecounterOn-Chip Cell StoreSRAM1InterfaceControl Cell ProcessorPacket ReassemblerRAD FPGANID FPGAExtract IP HeadersRemap VCIs for IP packetsLCSWRequestGrant01000000111111111applied research laboratoryapplied research laboratoryDavid E. TaylorPerformance Evaluation Used gate-l
5、evel simulation with ModelSim 100 MHz system clock Configured a FIPL Engine Controller to enable one to eight FIPL engines based on the contents of a control cell Initialized tree bitmap data structure with 16,564 entries from the Mae-West routing table (July 12, 2001 snapshot) Measured lookup laten
6、cy and throughput for test sequences of 2048 random destination addresses Addresses stored in on-chip memory read by FIPL Engine Controller Measured lookup latency and throughput for various update loads3applied research laboratoryapplied research laboratoryDavid E. TaylorThroughput and latency perf
7、ormance0123456789101112345678 # of FIPL enginesMillions of lookups per second010020030040050060070080090010001100Average Lookup Latency (ns)TheoreticalWorst-case Throughput Mae West Throughput TheoreticalWorst-case Avg. Lookup Latency Mae West Avg. Lookup Latencyapplied research laboratoryapplied re
8、search laboratoryDavid E. TaylorUpdate performance0123456789101112345678 # of FIPL enginesMillions of lookups per second1,000 updates per second 10,000 updates per second 100,000 updates per second No updates4applied research laboratoryapplied research laboratoryDavid E. TaylorPerformance on WU Rese
9、arch Platform Based on results, a 4 engine configuration was targeted to the WUGS/FPX research platform Sustained 1.988 Gb/s throughput on single-cell packets = 4.7 M packets/sec?Limited by 2 Gb/s switch interface of FPX (32-bit at 62.5 MHz)?Verified using bandwidth monitoring software, the cell mul
10、tiplying feature of the WUGS, and four traffic sources sending at different rates with corresponding 24-bit prefix entries in the route table Utilizes only 8% of available logic resources and 12.5% of on- chip memory resources?4 FIPL Engines and FIPL Engine Controller utilizes 6% of logic resources?
11、FIPL Wrapper utilizes 2% of logic resources and 12.5% of on-chip memory resourcesapplied research laboratoryapplied research laboratoryDavid E. TaylorCurrent Work: MSR IntegrationControl Path Data PathSRAM UpdatesDQ Status & Rate ControlRegister Set Updates & StatusCCPSRAMSRAMRegister SetFIPLQ-MgrMg
12、mt FiltersISAROSARPacket Storage Manager (includes free space list)SDRAMSDRAMPkt-ptr Shim HeaderHdr update Ref. counter Discard pkt.LCSWLCSWAAL0O-SWAAL55applied research laboratoryapplied research laboratoryDavid E. TaylorDefault FIPL Configuration Current FIPL Wrapper configured for future MSR inte
13、gration (all parameters modifiable via control cell) Listens for IP traffic on 4 sub-ports (SP0 SP3) Sub-port VCI determined by an input base VCI (Ibase_VCI) and a sub-port index (SPI)?Sub-port VCI = Ibase_VCI + SPI Defaults:?Ibase_VCI = 0x80 (128)?SP0 = 0, SP1 = 1, SP2 = 2, SP3 = 3?SP0_VCI = 0x80 (
14、128), SP1_VCI = 0x81 (129), Similar operation for outgoing VC resolution For current use, explicitly specify outgoing VCI as Next Hopapplied research laboratoryapplied research laboratoryDavid E. TaylorReferencesScalable IP Lookup for Programmable Routers , David E. Taylor, John W. Lockwood, Todd Sp
15、roull, Jonathan S. Turner, David B. Parlour, WUCS-01-33, 10/01.Generalized RAD Module Infrastructure of the Field Programmable Port Extender (FPX) Version 2.0 , David E. Taylor, John W. Lockwood, Naji Naufel, WUCS-TM-01-16, 7/01.Generalized RAD Module Interface Specification of the Field Programmabl
16、e Port Extender (FPX) Version 2.0 , David E. Taylor, John W. Lockwood, Sarang Dharmapurikar, WUCS-TM-01-15, 7/01.FPX Website: www.arl.wustl.edu/arl/projects/fpx6applied research laboratoryapplied research laboratoryDavid E. TaylorFIPL Switch Initializationapplied research laboratoryapplied research laboratoryDavid E. TaylorFIPL Switch Initialization Switch Configuration - GBNSC Restart Switch Configuration - Switch Reset Switch Config
