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1、Copyright 2007. All rights reserved. ARM DAI0179BApplication Note 179Cortex-M3 Embedded Software DevelopmentReleased on: March 2007Application Note 1792Copyright 2007. All rights reserved.ARM DAI0179BApplication Note 179 Cortex-M3 Embedded Software DevelopmentCopyright 2007. All rights reserved.Rele
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6、ubsidiaries” as appropriate.Confidentiality StatusThis document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.Product St
7、atusThe information in this document is final, that is for a developed product.Web Addresshttp:/Table 1 Change historyDateIssueChangeJanuary 2007AFirst release (withdrawn)March 2007BSecond releaseApplication Note 179ARM DAI0179BCopyright 2007. All rights reserved.31The Cortex-M3This application note
8、 introduces the main features of the ARM Cortex-M3 processor and describes different aspects of developing software for it. It also covers the migration of existing ARM projects to the Cortex-M3 platform.The ARM Cortex-M3 is a high performance, low cost and low power 32-bit RISC processor. The Corte
9、x-M3 processor only executes Thumb-2 instructions. It does not support the ARM instruction set. The Cortex-M3 processor is based on the ARM architecture v7-M and has an efficient Harvard 3-stage pipeline core. It also features hardware divide and low-latency Interrupt Service Routine(ISR) entry and
10、exit.As well as the CPU core, the Cortex-M3 processor includes a number of other components. These include a Nested Vectored Interrupt Controller (NVIC), an optional Memory Protection Unit (MPU), Timer, Debug Access Port (DAP) and optional Embedded Trace Macrocell (ETM). The Cortex-M3 also has a fix
11、ed memory map.1.1Nested Vectored Interrupt Controller (NVIC)Depending on the implementation used by the silicon manufacturer, the NVIC can support up to 240 external interrupts with up to 256 different priority levels that can be dynamically reprioritized. It supports both level and pulse interrupt
12、sources. The processor state is automatically saved by hardware on interrupt entry and is restored on interrupt exit. The NVIC also supports tail-chaining of interrupts.The use of an NVIC in the Cortex-M3 means that the vector table for a Cortex-M3 is very different to previous ARM cores. The Cortex
13、-M3 vector table contains the address of the exception handlers and ISR, not instructions as most other ARM cores do. The initial stack pointer and the address of the reset handler must be located at 0x0 and 0x4 respectively. These values are then loaded into the appropriate CPU registers at reset.1
14、.2Memory Protection Unit (MPU)The MPU is an optional component of the Cortex-M3. If included, it provides support for protecting regions of memory through enforcing privilege and access rules. It supports up to eight different regions, each of which can be split into a further eight equal-size sub-r
15、egions.1.3Debug Access Port (DAP)The DAP uses an AHB-AP interface to communicate with the processor and other peripherals. There are two different supported implementations of the Debug Port, the Serial Wire JTAG Debug Port (SWJ-DP) and the Serial Wire Debug Port (SW-DP). Your Cortex-M3 implementati
16、on might contain either of these depending on the implementation used by your silicon manufacturer.1.4Memory mapUnlike most previous ARM cores, the overall layout of the memory map of a device based around the Cortex-M3 is fixed. This allows easy porting of software between different systems based on the Cortex-M3. The address space is split into a number of different sections. This is shown in Figure 1 on page 4 and described in Tab