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1、EECS 141Fall 1999Discussion Session Week #19/1/99Tips for using HspiceI. Getting Started Setup the environment: source /usr/eesww/HSPICE/98.2/bin/cshrc.meta Run the simulator on your input file: hspice filename.sp ! filename.lis Use the waveform viewer to see the output awaves Input files must have
2、the extension .sp for the waveform viewer to work. Also, the input file must have “.OPTION POST=2” specified. Waveforms can be printed by choosing Tools - Print. View the online documentation acroread /usr/eesww/HSPICE/98.2/docs/hspice.pdf without it the current design complexity would not have been
3、 achievable. Design tools include simulation at the various complexity levels, design verification, layout generation, and design synthesis. An overview of these tools and design methodologies is given in Chapter 8 of this textbook. Furthermore, to avoid the redesign and reverification of frequently
4、 used cells such as basic gates and arithmetic and memory modules, designers most often resort to cell libraries. These libraries contain not only the layouts, but also provide complete docu- mentation and characterization of the behavior of the cells. The use of cell libraries is, forn+n+SG D+DEVIC
5、ECIRCUITGATEMODULESYSTEMFigure 1.6Design abstraction levels in digital circuits.chapter1.fm Page 16 Friday, January 18, 2002 8:58 AMSection 1.2Issues in Digital Integrated Circuit Design17instance, apparent in the layout of the Pentium 4 processor (Figure 1.5b). The integer and floating-point unit,
6、just to name a few, contain large sections designed using the so- called standard cell approach. In this approach, logic gates are placed in rows of cells of equal height and interconnected using routing channels. The layout of such a block can be generated automatically given that a library of cell
7、s is available. The preceding analysis demonstrates that design automation and modular design practices have effectively addressed some of the complexity issues incurred in contempo- rary digital design. This leads to the following pertinent question. If design automation solves all our design probl
8、ems, why should we be concerned with digital circuit design at all? Will the next-generation digital designer ever have to worry about transistors or para- sitics, or is the smallest design entity he will ever consider the gate and the module? The truth is that the reality is more complex, and vario
9、us reasons exist as to why an insight into digital circuits and their intricacies will still be an important asset for a long time to come. First of all, someone still has to design and implement the module libraries. Semi- conductor technologies continue to advance from year to year. Until one has
10、devel- oped a fool-proof approach towards “porting” a cell from one technology to another, each change in technologywhich happens approximately every two yearsrequires a redesign of the library. Creating an adequate model of a cell or module requires an in-depth understanding of its internal operati
11、on. For instance, to identify the dominant performance parame- ters of a given design, one has to recognize the critical timing path first. The library-based approach works fine when the design constraints (speed, cost or power) are not stringent. This is the case for a large number of application-s
12、pecific designs, where the main goal is to provide a more integrated system solution, and performance requirements are easily within the capabilities of the technology. Unfortunately for a large number of other products such as microprocessors, success hinges on high performance, and designers there
13、fore tend to push technology to its limits. At that point, the hierarchical approach tends to become somewhat less attractive. To resort to our previous analogy to software methodologies, a program- mer tends to “customize” software routines when execution speed is crucial; com- pilersor design tool
14、sare not yet to the level of what human sweat or ingenuity can deliver. Even more important is the observation that the abstraction-based approach is only correct to a certain degree. The performance of, for instance, an adder can be sub- stantially influenced by the way it is connected to its envir
15、onment. The interconnec- tion wires themselves contribute to delay as they introduce parasitic capacitances, resistances and even inductances. The impact of the interconnect parasitics is bound to increase in the years to come with the scaling of the technology. Scaling tends to emphasize some other
16、 deficiencies of the abstraction-based model. Some design entities tend to be global or external (to resort anew to the software analogy). Examples of global factors are the clock signals, used for synchronization in a digital design, and the supply lines. Increasing the size of a digital design has achapter1.fm Page 17 Friday, January 18, 2002 8:58 AM18INTRODUCTIONChapter 1profound effect on these global signals. For instance, connecting more cells to a sup-
