《adn2913特性参数选型详解及样片》由会员分享，可在线阅读，更多相关《adn2913特性参数选型详解及样片（36页珍藏版）》请在金锄头文库上搜索。
1、ADNADN2 2913913 特性特性参数参数选型选型及及样片样片信息信息详解详解 SLICE ADJUST LOS THRESH TXD 11777-001 Data Recovery IC with Integrated Limiting Amp/EQ Data Sheet ADN2913 FEATURES Serial data input: 6.5 Mbps to 8.5 Gbps No reference clock required Exceeds SONET/SDH requirements for jitter transfer/ generation/tolerance Q
2、uantizer sensitivity: 6.3 mV typical (limiting amplifier mode) Optional limiting amplifier, equalizer (EQ), and 0 dB EQ inputs Programmable jitter transfer bandwidth to support G.8251 OTN Programmable slice level Sample phase adjust (5.65 Gbps or greater) Output polarity invert Programmable LOS thre
3、shold via I2C I2C interface to access optional features Loss of signal (LOS) alarm (limiting amplifier mode only) Loss of lock (LOL) indicator PRBS generator/detector Application-aware power 352 mW at 8.5 Gbps, equalizer mode, no clock output 380 mW at 6.144 Gbps, limiting amplifier mode, no clock o
4、utput 340 mW at 622 Mbps, 0 dB EQ mode, no clock output Power supplies: 1.2 V, flexible 1.8 V to 3.3 V, and 3.3 V 4 mm 4 mm, 24-lead LFCSP APPLICATIONS SONET/SDH OC-1/OC-3/OC-12/OC-48 and all associated FEC rates 1GE, 1GFC, 2GFC, 4GFC, 8GFC, CPRI OS/L.6 up to OS/L.60 Any rate regenerators/repeaters
5、GENERAL DESCRIPTION The ADN2913（样片申请信息查询：） provides the receiver functions of quantization, signal level detection, and clock and data recovery for continuous data rates from 6.5 Mbps to 8.5 Gbps. The ADN2913 automati- cally locks to all data rates without the need for an external reference clock or
6、 programming. ADN2913 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation, and jitter tolerance. The ADN2913 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting am
7、plifier, equalizer, or 0 dB EQ at the input. The equalizer is adaptive or it can be manually set. The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level falls below a user- programmable threshold. The LOS detection circuit has hysteresis to prevent chatter
8、 at the LOS output. In addition, the input signal strength can be read through the I2C registers. The ADN2913 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features. The ADN2913 is available in a compact 4 mm 4 mm, 24-lead lead frame
9、chip scale package (LFCSP). All ADN2913 specifica- tions are defined over the ambient temperature range of 40C to +85C, unless otherwise noted. FUNCTIONAL BLOCK DIAGRAM REFCLKP/ REFCLKN DATOUTP/ CLKOUTP/ SCK SDA LOL (OPTIONAL) DATOUTN CLKOUTN I2C_ADDR I2C REGISTERS FREQUENCY ACQUISITION AND LOCK DET
10、ECTOR ADN2913 DATA RATE CML CLK DDR CML LOS LOS DETECT SAMPLE PHASE ADJUST FIFO N 2 PIN NIN 50 VCM FLOAT 2 50 I2C VCC LA 0dB EQ EQ I2C DATA SAMPLER Figure 1. RXCK AND LOOP FILTER PHASE SHIFTER CLOCK Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and relia
11、ble. However, no responsibilityis assumed by Analog Devices for its use, nor for anyinfringements of patents or other rightsofthird partiesthat may result fromitsuse. Specifications subjectto change without notice. No license is granted by implication or otherwise under any patent or patent rights o
12、f Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. Technical Support 国内外 65 家 IC 厂商免费样片查询：ICTry 样片申请网 Data Sheet Rev. 0 | Page 2 of 36 TABLE OF CONTENTS Features . 1 Applications . 1 General Description . 1 Functional Block Diagram . 1 Revision History . 2 Specifications. 3 Jitter Specifications . 4 Output and Timing Specifications . 6 Timing Diagrams. 8 Absolute Maximum Ratings. 9 Thermal Characteristics . 9 ESD Caution.
