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1、 InvenSense Inc. 1197 Borregas Ave, Sunnyvale, CA 94089 U.S.A. Tel: +1 (408) 988-7339 Fax: +1 (408) 988-8104 Website: Document Number: RM-MPU-6000A-00 Revision: 3.2 Release Date: 11/14/2011 CONFIDENTIAL the MPU-6000 supports SPI at up to 20MHz in addition to I2C, and has a single supply pin, VDD, w
2、hich is both the devices logic reference supply and the analog supply for the part. For more detailed information for the MPU-60X0 devices, please refer to the “MPU-6000 and MPU-6050 Product Specification”. MPU-6000/MPU-6050 Register Map and Descriptions Document Number: RM-MPU-6000A-00 Revision: 3.
3、2 Release Date: 11/14/2011 CONFIDENTIAL Registers 39, 42, and 45). For information regarding EXT_SENS_DATA registers, please refer to Registers 73 to 96. Note that the corresponding FIFO_EN bit (SLV3_FIFO_EN) is found in I2C_MST_CTRL (Register 36). Also note that Slave 4 behaves in a different manne
4、r compared to Slaves 0-3. Please refer to Registers 49 to 53 for further information regarding Slave 4 usage. Parameters: TEMP_FIFO_EN When set to 1, this bit enables TEMP_OUT_H and TEMP_OUT_L (Registers 65 and 66) to be written into the FIFO buffer. XG_ FIFO_EN When set to 1, this bit enables GYRO_
5、XOUT_H and GYRO_XOUT_L (Registers 67 and 68) to be written into the FIFO buffer. YG_ FIFO_EN When set to 1, this bit enables GYRO_YOUT_H and GYRO_YOUT_L (Registers 69 and 70) to be written into the FIFO buffer. ZG_ FIFO_EN When set to 1, this bit enables GYRO_ZOUT_H and GYRO_ZOUT_L (Registers 71 and
6、 72) to be written into the FIFO buffer. ACCEL_ FIFO_EN When set to 1, this bit enables ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L, ACCEL_ZOUT_H, and ACCEL_ZOUT_L (Registers 59 to 64) to be written into the FIFO buffer. SLV2_ FIFO_EN When set to 1, this bit enables EXT_SENS_DATA register
7、s (Registers 73 to 96) associated with Slave 2 to be written into the FIFO buffer. SLV1_ FIFO_EN When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96) associated with Slave 1 to be written into the FIFO buffer. SLV0_ FIFO_EN When set to 1, this bit enables EXT_SENS_DATA regist
8、ers (Registers 73 to 96) associated with Slave 0 to be written into the FIFO buffer. Note: For further information regarding the association of EXT_SENS_DATA registers to particular slave devices, please refer to Registers 73 to 96. MPU-6000/MPU-6050 Register Map and Descriptions Document Number: RM
9、-MPU-6000A-00 Revision: 3.2 Release Date: 11/14/2011 CONFIDENTIAL & PROPRIETARY 19 of 50 4.13 Register 36 I2C Master Control I2C_MST_CTRL Type: Read/Write Register (Hex) Register (Decimal) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 24 36 MULT _MST_EN WAIT _FOR_ES SLV_3 _FIFO_EN I2C_MST _P_NSR I2C_MST_C
10、LK3:0 Description: This register configures the auxiliary I2C bus for single-master or multi-master control. In addition, the register is used to delay the Data Ready interrupt, and also enables the writing of Slave 3 data into the FIFO buffer. The register also configures the auxiliary I2C Masters
11、transition from one slave read to the next, as well as the MPU-60X0s 8MHz internal clock. Multi-master capability allows multiple I2C masters to operate on the same bus. In circuits where multi-master capability is required, set MULT_MST_EN to 1. This will increase current drawn by approximately 30A
12、. In circuits where multi-master capability is required, the state of the I2C bus must always be monitored by each separate I2C Master. Before an I2C Master can assume arbitration of the bus, it must first confirm that no other I2C Master has arbitration of the bus. When MULT_MST_EN is set to 1, the
13、 MPU-60X0s bus arbitration detection logic is turned on, enabling it to detect when the bus is available. When the WAIT_FOR_ES bit is set to 1, the Data Ready interrupt will be delayed until External Sensor data from the Slave Devices are loaded into the EXT_SENS_DATA registers. This is used to ensu
14、re that both the internal sensor data (i.e. from gyro and accel) and external sensor data have been loaded to their respective data registers (i.e. the data is synced) when the Data Ready interrupt is triggered. When the Slave 3 FIFO enable bit (SLV_3_FIFO_EN) is set to 1, Slave 3 sensor measurement
15、 data will be loaded into the FIFO buffer each time. EXT_SENS_DATA register association with I2C Slaves is determined by I2C_SLV3_CTRL (Register 48). For further information regarding EXT_SENS_DATA registers, please refer to Registers 73 to 96. The corresponding FIFO_EN bits for Slave 0, Slave 1, an
16、d Slave 2 can be found in Register 35. The I2C_MST_P_NSR bit configures the I2C Masters transition from one slave read to the next slave read. If the bit equals 0, there will be a restart between reads. If the bit equals 1, there will be a stop followed by a start of the following read. When a write transaction follows a read transaction, the stop followed by a start of the successive wr
