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1、module clock (clk,reset,seg,sel);input clk; input reset; output seg; output sel;/- reg 23:0Q; /1s reg clk_div_1; wire clk_1s;always (posedge clk or negedge reset)beginif (!reset) Q=24d0;else if (Q24d9999999) Q=Q+1b1;else Q=24d0;endalways (posedge clk or negedge reset)beginif (!reset) clk_div_1=1b1;e
2、lse if (Q = 24d9999999) clk_div_1=clk_div_1;endassign clk_1s=clk_div_1; /- reg 27:0W; /10s reg clk_div_2; wire clk_10s;always (posedge clk or negedge reset)beginif (!reset) W=28d0;else if (W28d99999990) W=W+1b1;else W=28d0;endalways (posedge clk or negedge reset)beginif (!reset) clk_div_2=1b1;else i
3、f (W = 28d99999990) clk_div_2=clk_div_2;endassign clk_10s=clk_div_2; /- reg 29:0E; /60s reg clk_div_3; wire clk_60s;always (posedge clk or negedge reset)beginif (!reset) E=30d0;else if (E30d599999940) E=E+1b1;else E=30d0;endalways (posedge clk or negedge reset)beginif (!reset) clk_div_3=1b1;else if
4、(E = 30d599999940) clk_div_3=clk_div_3;endassign clk_60s=clk_div_3;/- reg 33:0R; /600s reg clk_div_4; wire clk_600s;always (posedge clk or negedge reset)beginif (!reset) R=34d0;else if (R34d5999999400) R=R+1b1;else R=34d0;endalways (posedge clk or negedge reset)beginif (!reset) clk_div_4=1b1;else if
5、 (R = 24d5999999400) clk_div_4=clk_div_4;endassign clk_600s=clk_div_4; /- reg 16:0A; reg clk_div_r; wire clk_div;always (posedge clk or negedge reset)/freq_division 30*4=120beginif (!reset) A=17d0;else if (A17d83334) A=A+1b1;/20000000/2/120=83334 0-83334 else A=17d0;endalways (posedge clk or negedge
6、 reset)beginif (!reset) clk_div_r=1b1;else if (A = 17d83334) clk_div_r=clk_div_r;endassign clk_div=clk_div_r; /- reg 2:0T;always (posedge clk_div or negedge reset)/six circle beginif (!reset) T=3d0;else if (T3d3) T=T+1b1;/0-3else T=3d0;end /- reg 3:0sel; /scan seg,sel reg 7:0seg;always (T)beginif (T
7、=3b000) sel=4b1110;else if (T=3b001) sel=4b1101; else if (T=3b010) sel=4b1011;else if (T=3b011) sel=4b0111;else sel=4b1110;endalways (T)beginif (T=3b000) seg=Y1;else if (T=3b001) seg=Y2;else if (T=3b010) seg=Y3;else if (T=3b011) seg=Y4;else seg= Y1;end /- parameter seg0 = 8b11000000, /seg 0-9seg1 =
8、8b11001111,seg2 = 8b10100100,seg3 = 8b10110000,seg4 = 8b10011001,seg5 = 8b10010010,seg6 = 8b10000010,seg7 = 8b11111000,seg8 = 8b10000000,seg9 = 8b10011000;/- reg 3:0Q1; reg 7:0Y1;always (posedge clk_1s or negedge reset)/Asy_rstbeginif (!reset) Q1=4d0;else if (Q14d9) Q1=Q1+1b1;/0-9else Q1=4d0;endalwa
9、ys (Q1)/circlebeginif (Q1=4d0) Y1=seg0;else if (Q1=4d1) Y1=seg1;else if (Q1=4d2) Y1=seg2;else if (Q1=4d3) Y1=seg3;else if (Q1=4d4) Y1=seg4;else if (Q1=4d5) Y1=seg5;else if (Q1=4d6) Y1=seg6;else if (Q1=4d7) Y1=seg7;else if (Q1=4d8) Y1=seg8;else if (Q1=4d9) Y1=seg9;else Y1=seg0;end /- reg 2:0Q2; reg 7
10、:0Y2;always (posedge clk_10s or negedge reset)/Asy_rstbeginif (!reset) Q2=3d0;else if (Q23d5)Q2=Q2+1b1; /0-5else Q2=3d0;endalways (Q2)/circlebeginif (Q2=3d0) Y2=seg0;else if (Q2=3d1) Y2=seg1;else if (Q2=3d2) Y2=seg2;else if (Q2=3d3) Y2=seg3;else if (Q2=3d4) Y2=seg4;else if (Q2=3d5) Y2=seg5;else Y2=s
11、eg0;end /- reg 3:0Q3; reg 7:0Y3;always (posedge clk_60s or negedge reset)/Asy_rstbeginif (!reset) Q3=4d0;else if (Q34d9) Q3=Q3+1b1;/0-9else Q3=4d0;endalways (Q3)/circlebeginif (Q3=4d0) Y3=seg0;else if (Q3=4d1) Y3=seg1;else if (Q3=4d2) Y3=seg2;else if (Q3=4d3) Y3=seg3;else if (Q3=4d4) Y3=seg4;else if
12、 (Q3=4d5) Y3=seg5;else if (Q3=4d6) Y3=seg6;else if (Q3=4d7) Y3=seg7;else if (Q3=4d8) Y3=seg8;else if (Q3=4d9) Y3=seg9;else Y3=seg0;end/-reg 2:0Q4; reg 7:0Y4;always (posedge clk_600s or negedge reset)/Asy_rstbeginif (!reset) Q4=3d0;else if (Q43d5) Q4=Q4+1b1;/0-5else Q4=3d0;endalways (Q4)/circlebeginif (Q4=3d0) Y4=seg0;else if (Q4=3d1) Y4=seg1;else if (Q4=3d2) Y4=seg2;else if (Q4=3d3) Y4=seg3;else if (Q4=3d4) Y4=seg4;else if (Q4=3d5) Y4=seg5;else Y4=seg0;end /-endmodule
