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1、module fenpin(clk_48m,reset,out_door,addr,data,data_rd,rd,rw,Grating_a,Grating_b); input clk_48m,data_rd,reset,rd,rw,Grating_a,Grating_b; input 8:0addr;output out_door;inout 7:0data;reg flag; reg 23:0step; reg 23:0pul_counter; reg 5:0clk_div1m; reg 23:0den; reg 23:0counter; reg 23:0counter_now; reg
2、19:0Grating_counter; reg 7:0com; reg 7:0databuff; reg out=0; reg data_link; reg direct;assign data=data_link?databuff:8bzzzzzzzz;assign out_door=outalways(posedge clk_48m) if(clk_div1mden)begin counter_now=counter_now-1;endelsebeginendendelsebeginend endalways (posedge clk_48m) begin if(!reset) begi
3、n counter=0; endelse if(com0:0=1b1)beginif(counter=counter_now-1)begin counter=0;out=out;end elsebegin counter=counter+1;endendelsebeginend endalways (posedge out) begin if(!reset) beginflag=1; pul_counter=0; end else begin if(pul_counter=step) begin flag=0; pul_counter=0; end else pul_counter=pul_c
4、ounter+1; end endalways(posedge Grating_a) if(Grating_b=1)direct=1;else direct=0;always(posedge Grating_a) begin if(!reset) Grating_counter=0;else if(direct=1)Grating_counter=Grating_counter+1;else Grating_counter=Grating_counter-1; endalways (posedge clk_48m) begin if(!reset)begindata_link=1b0;ende
5、lse if(rw)begindata_link=1b1;endendalways ( posedge clk_48m ) beginif(!reset)beginstep=0;den=0;com=0;endelse if(data_rd3b001 : den15:8= data;3b010 : den23:16=data;3b011 : step7:0= data;3b100 : step15:8= data;3b101 : step23:16=data; 3b110 : com7:0=data;/数据传送完毕endcaseelse beginendendalways (posedge cl
6、k_48m) beginif(!reset)begindatabuff=0;endelse if(data_rd8h01:databuff=den15:8;8h02:databuff=den23:16;8h03:databuff=step7:0;8h04:databuff=step15:8;8h05:databuff=step23:16;8h06:databuff=com7:0;8h07:databuff=Grating_counter7:0;8h08:databuff=Grating_counter15:8;8h09:databuff=4h0,Grating_counter19:16;endcaseelsebeginendend endmodule
