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1、1复旦大学计算机科学技术学院复旦大学计算机科学技术学院计算机原理计算机原理期末考试试卷期末考试试卷A A 卷卷 共共 1313 页页课程代码：课程代码：INFO130054.01-02INFO130054.01-02 _ _考试形式：开卷考试形式：开卷 2010 年 6 月（本试卷答卷时间为 100 分钟，答案必须写在答卷上，做在试卷上无效）专业学号姓名成绩 题号1234567总分得分Problem 1.Number Conversion: IEEE 754 single precision 32-bit float standard representation with a little
2、change is illustrated below. Normalized: (-1)sign * (1.fraction) * 2exponent-127 (exp=1 to 254)Denormalized: (-1)sign * (0.fraction) * 2-126(when exp=0, fraction0)Zero: all 0s in all 3 fields1)Convert the number -35.390625 into this changed IEEE 754 FP single precision representation (in hex). (-35.
3、390625)10 = (0x )1622)With changed 32-bit float representation, what is the equivalent value as a decimal number? A: (0011 1111 0001 0000 0000 0000 0000 0000)2B: (0000 0000 0011 0101 0000 0000 0000 0000)23)Calculate the sum of (35.390625)10 and (0011 1111 0001 0000 0000 0000 0000 0000)2 using change
4、d 32-bit float representation, and then round the sum (in binary number value, e.g. (1000.11)2 for (8.75)10 ) to 4 bits to the right of the binary point by both round-up and round-down. Give your steps detailed. 4)Given three numbers f1, f2 and f3 of this changed 32-bit representation, none of them
5、equals +, - or NaN, and x is signed 32-complement representation. Please tell whether two C expressions below are always true. If yes, give the reason in detail; If no, give a counterexample and show the detail computation steps to get false. A: x = = (int) (float) x; B: (f1 f2) = = (f1 + f3) (f2 +
6、f3) 3Please read the following C code and assembly code and then fill in the blanks. #include int p54 = 43,56,78,69,- 7,89,7,23,24,36,88,67, 12,56,78,90,62,93,-78,9; int main(void)int result = cal(5,4);printf(“The result is %dn“, result); int cal(int a, int b)int i;int result=0;for ( i = 0; i */ int
7、 logicalShift (int x, int n) int mask= 0x7f _4_) _5_ ( mask (_6_); 9Problem 5.A computer has main memory(MM) with 256K words size, and a 8K words set associative cache. Each set of cache has 4 pages with 64 words in each page. Suppose the cache is initially empty. CPU read data from MM at the addres
8、s of 0, 1, 2, , 8447(When read misses in cache, the full page containing destination bytes is written into the cache first and read from the cache). This reading process repeats for 20 times. We know that cache access time is 10% of that of MM. LRU replacement policy is used on cache. Please figure
9、out how many times the total reading operations will be faster using cache compared with no cache? You must write out complete steps with necessary descriptions.Problem 6.You are given the following definitions:struct pc int x; int y; int z; ; struct pc sq1616; int i,j;Assume the following:sizeof(in
10、t) = 4.sq begins at memory address 0.The machine has a 2048-byte direct-mapped data cache with 32-byte blocks.The cache is initially empty.The only memory accesses are to the entries of the array sq. Variables i and j are stored in registers.10Determine the cache performance of the following code:fo
11、r (i = 0; i 16; i +) for (j = 0; j 16; j +) sqij.x = 0; sqij.y = 0; sqij.z = 1; 1) What is the total number of writes?2) What is the total number of writes that miss the cache?Given the above assumptions, determine the cache performance of the following code:for (i = 0; i 16; i +) for (j = 0; j 16;
12、j +) sqji.x = 0; sqji.y = 0; sqji.z = 1; 3) What is the total number of writes?4) What is the total number of writes that miss the cache11Problem 7.Virtual Address TranslationWe consider a virtual address system with the following parameters. The memory is byte addressable. Virtual addresses are 20
13、bits wide. Physical addresses are 16 bits wide. The page size is 4096 bytes. The TLB is 4-way set associative with 16 total entries. In the following tables, all numbers are given in hexadecimal. The contents of the TLB and the page table for the first 16 virtual pages are as follows. If a VPN is no
14、t listed in the page table, assume it generates a page fault.TLBPage Table IndexTagPPNValidVPNPPNValid 003B10071 07600181 28310291 01F003A1 131010460 12300530 07E10610 0B110780 22AA00820 11100930 1F810A11 07510B61 307310CC1 3FF00DD0 10D00EE0 32000FD11)In the four rows below, mark the bits that const
15、itute the indicated part of the virtual address with an X. Leave the remaining bits of each row blank.Virtual Page Number191817161514131211109876543210VPN12Virtual Page Offset191817161514131211109876543210VPOTLB Tag191817161514131211109876543210TLBTTLB Index191817161514131211109876543210TLBI2)For the virtual address 0x7E37C, indicate the physical address and various results of the translation. If there is a page fault, enter “” for the PPN and Physical Address. All answers should be given in hexadecimal.Virtual Address (one bit per box)1918171615141312111098765
