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1、 Orcad LayoutGetting StartedCadence PCB Systems Division 13221 SW 68th Parkway, Suite 200 Portland, OR 97223Copyright 1985-2000 Cadence Design Systems, Inc. All rights reserved.TrademarksAllegro, Ambit, BuildGates, Cadence, Cadence logo, Concept, Diva, Dracula, Gate Ensemble, NC Verilog, OpenBook on
2、line documentation library, Orcad, Orcad Capture, PSpice, SourceLink online customer support, SPECCTRA, Spectre, Vampire, Verifault-XL, Verilog, Verilog-XL, and Virtuoso are registered trademarks of Cadence Design Systems, Inc.Affirma, Assura, Cierto, Envisia, Mercury Plus, Quickturn, Radium, Silico
3、n Ensemble, and SPECCTRAQuest are trademarks of Cadence Design Systems, Inc.Alanza is a service mark of Cadence Design Systems, Inc.All other brand and product names mentioned herein are used for identification purposes only and are registered trademarks, trademarks, or service marks of their respec
4、tive holders.Part Number 60-30-645Second edition 31 May 2000Cadence PCB Systems Division (PSD) offices PSD main office (Portland)(503) 671-9500 PSD Irvine office(949) 788-6080 PSD Japan office81-45-682-5770 PSD UK office44-1256-381-400PSD customer support(877) 237-4911PSD web PSD customer support w
5、eb PSD customer support email you begin vii Welcome to OrCAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii How to use this guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii Symbols and conventions . . . . . . . . . . . . . . . . . . . . . . . . viiiBoard design
6、 tasks 1Chapter 1Typical board design tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Board design flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Creating a board 5Chapter 2Methods to create a board . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Creating
7、 a board from scratch . . . . . . . . . . . . . . . . . . . . . . . 7 Creating a board using a board template . . . . . . . . . . . . . . . . . 8 Importing a board using the DXF to Layout translator . . . . . . . . . 10 Importing a board using the PRO-E to Layout translator . . . . . . . . 12Setting
8、 up board parameters 15Chapter 3Creating a board outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Setting units of measurement . . . . . . . . . . . . . . . . . . . . . . . . . 17 Setting system grids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Adding mounting
9、holes to a board . . . . . . . . . . . . . . . . . . . . . . 21 Defining the layer stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Defining global spacing values . . . . . . . . . . . . . . . . . . . . . . . . . 23 Defining padstacks . . . . . . . . . . . . . . . . . . . . . . . .
10、 . . . . . . . 25 Using vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Placing components 29Chapter 4Preparing the board for component placement . . . . . . . . . . . . . . . 30 Checking the board, place, and insertion outlines . . . . . . . . . . . . 30 Checking th
11、e place grid . . . . . . . . . . . . . . . . . . . . . . . . . . . 31ContentsivChecking mirror layers and library layers . . . . . . . . . . . . . . . 32 Weighting and color-coding nets . . . . . . . . . . . . . . . . . . . . . 33 Checking gate and pin information . . . . . . . . . . . . . . . . . .
12、 . 34 Securing preplaced components on the board . . . . . . . . . . . . . 35 Creating height or group keepins and keepouts . . . . . . . . . . . . 36 Loading a placement strategy file . . . . . . . . . . . . . . . . . . . . 38 Disabling the power and ground nets . . . . . . . . . . . . . . . . . .
13、38 Placing components manually . . . . . . . . . . . . . . . . . . . . . . . . 39 Selecting the next components for placement . . . . . . . . . . . . . 40 Placing component groups . . . . . . . . . . . . . . . . . . . . . . . . 40 Minimizing connections to optimize placement . . . . . . . . . . . . 41 Checking placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Using Placement Spacing Violations . . . . . . . . . . . . . . . . . . . 42 Using the density grap
