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1、简易时钟的设计 1.分频电路的设计 -实体名：fen100 -功 能：对输入时钟进行 24000 分频，得到 100Hz 信号， - 作为数码显示管位扫描信号 -接 口：clk -时钟输入 - qout-100Hz 输出信号-library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;entity fen100 is port (clk:in std_logic;rst:in std_logic;qout:out std_logic ); end
2、 fen100;architecture behave of fen100 is constant counter_len:integer:=23999; beginprocess(clk,rst)variable cnt:integer range 0 to counter_len;beginif(rst=0)thencnt:=0;elsif clkevent and clk=1 thenif cnt=counter_len thencnt:=0;elsecnt:=cnt+1;end if;case cnt is when 0 to counter_len/2=qoutqoutqoutqou
3、t=1;end case;end if;end process;end behave;2.60 进制 -功 能：60 进制计数器 -接 口：clk -时钟输入 - qout1-个位 BCD 输出 - qout2-十位 BCD 输出 - carry-进位信号输出-library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;entity fen60 is port (clk : in std_logic;rst : in std_logic;qout
4、1 : out std_logic_vector(3 downto 0);qout2 : out std_logic_vector(3 downto 0);carry : out std_logic ); end fen60;architecture behave of fen60 is signal tem1:std_logic_vector(3 downto 0); signal tem2:std_logic_vector(3 downto 0); beginprocess(clk,rst)beginif(rst=0)thentem1=“0000“;tem2=“0000“;elsif cl
5、kevent and clk=1 then if tem1=“1001“ thentem1=“0000“;if tem2=“0101“ thentem2=“0000“;carry=1;elsetem2=tem2+1;carry=0;end if;elsetem1=tem1+1;end if;end if;qout1=tem1;qout2=tem2;end process; end behave; 3.24 进制的设计 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_
6、logic_arith.all;entity fen24 is port (clk : in std_logic;rst : in std_logic;qout1 : out std_logic_vector(3 downto 0);qout2 : out std_logic_vector(3 downto 0);carry : out std_logic ); end fen24;architecture behave of fen24 is signal tem1:std_logic_vector(3 downto 0); signal tem2:std_logic_vector(3 do
7、wnto 0); beginprocess(clk,rst)beginif(rst=0)thentem1=“0010“;tem2=“0001“;elsif clkevent and clk=1 then if (tem2=“0010“ and tem1=“0011“) thentem1=“0000“;tem2=“0000“;carry=1;elsecarry=0;if tem1=“1001“ thentem1=“0000“;if tem2=“1001“ thentem2=“0000“;elsetem2=tem2+1;end if;elsetem1=tem1+1;end if;end if;en
8、d if;qout1=tem1;qout2=tem2;end process; end behave; 4.数码管显示 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;entity fen24 is port (clk : in std_logic;rst : in std_logic;qout1 : out std_logic_vector(3 downto 0);qout2 : out std_logic_vector(3 dow
9、nto 0);carry : out std_logic ); end fen24;architecture behave of fen24 is signal tem1:std_logic_vector(3 downto 0); signal tem2:std_logic_vector(3 downto 0); beginprocess(clk,rst)beginif(rst=0)thentem1=“0010“;tem2=“0001“;elsif clkevent and clk=1 then if (tem2=“0010“ and tem1=“0011“) thentem1=“0000“;
10、tem2=“0000“;carry=1;elsecarry=0;if tem1=“1001“ thentem1=“0000“;if tem2=“1001“ thentem2=“0000“;elsetem2=tem2+1;end if;elsetem1=tem1+1;end if;end if;end if;qout1=tem1;qout2=tem2;end process; end behave; 5.数码管显示编码 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_
11、logic_arith.all;entity fen24 is port (clk : in std_logic;rst : in std_logic;qout1 : out std_logic_vector(3 downto 0);qout2 : out std_logic_vector(3 downto 0);carry : out std_logic ); end fen24;architecture behave of fen24 is signal tem1:std_logic_vector(3 downto 0); signal tem2:std_logic_vector(3 do
12、wnto 0); beginprocess(clk,rst)beginif(rst=0)thentem1=“0010“;tem2=“0001“;elsif clkevent and clk=1 then if (tem2=“0010“ and tem1=“0011“) thentem1=“0000“;tem2=“0000“;carry=1;elsecarry=0;if tem1=“1001“ thentem1=“0000“;if tem2=“1001“ thentem2=“0000“;elsetem2=tem2+1;end if;elsetem1=tem1+1;end if;end if;en
13、d if;qout1=tem1;qout2=tem2;end process; end behave; 6.系统的整体设计VCCclkINPUTGNDrstINPUTsel5.0OUTPUTseg6.0OUTPUTclkrstqoutfen100inst2clkrstqoutfen1instclkrstqout13.0qout23.0carryfen60inst3clkrstqout13.0qout23.0carryfen60inst7clkrstqout13.0qout23.0carryfen24inst4clkrstqin13.0qin23.0qin33.0qin43.0qin53.0qin63.0qout3.0sel5.0selinst5qin3.0qout6.0decode47inst67位 位 位 位位 位 位 位 位 位40MHz位 位 位 位
