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1、原文：原文：This design take at MCS-51 monolithic integrated circuit as the core full use hardware source designs one kind of frequency meter, this frequency meter will be measured first that signal enlargement reshaping processing, turns satisfies TTL/which the monolithic integrated circuit I/O mouth acc
2、epts the CMOS compatible signal from monolithic integrated circuits T1 input port input direct summation pulse number, the monolithic integrated circuit interior timer fixed time is 1S, by now accumulated the pulse number namely for is measured the signal the frequency. Finally passes through monoli
3、thic integrated circuit processing to deliver to the lcd liquid crystal display monitor demonstration.Central Processing Unit DesignsThe CPU is the key component of a digital computer. Its purpose is to decode instruction received from memory and perform transfers, arithmetic, logic, and control ope
4、rations with data stored in internal registers, memory, or I/O interface units. Externally, the CPU provides one or more buses for transferring instructions, data, and control information to and from components connected to it. In the generic computer at the beginning of chapter 1, the CPU is a part
5、 of the processor and is heavily shaded. CPUs, however, may also appear in computers. Small, relatively simple computers called microcontrollers are used in computers and in other digital systems to perform limited or specialized tasks. For example, a microcontroller is present in the keyboard and i
6、n the monitor in the generic computer; thus, these components are also shaded. In such microcontrollers, the CPU may be quite different from those discussed in this chapter. The word lengths may be short (say, four or eight bits),the number of registers small, and the instruction sets limited. Perfo
7、rmance, relatively speaking, is poor, but adequate for the task. Most important, the cost of these microcontrollers is very low, making their use cost effective.In the following pages, we consider two computer CPUs, one for a complex instruction set computer (CISC) and the other for a reduced instru
8、ction set computer (RISC). After a detailed examination of the designs, we compare the performance of the two CPUs and present a brief overview of some methods used to enhance that performance. Finally, we relate the design ideas discussed to general digital system design.1、The complex instruction s
9、et computer The first design we present is for a complex instruction set computer with a non-pipelined datapath and microprogrammed control unit. We begin by describing the instruction set architecture, including the CPU register set, instruction formats, and addressing modes. The 1CISC nature of th
10、e instruction set architecture is demonstrated by its memory-to-memory access for data manipulation instructions, eight addressing modes, two instruction format lengths, and instructions that require significant sequences of operations for their execution.We design a datapath for implementing the CI
11、SC architecture. The datapath is based on the one initially described in Section 7-9 and incorporated into a CPU in section 8-10. modifications are made to the register file, the function unit, and the buses to support the present instruction set architecture.Once the datapath has been specified, a
12、control unit is designed to complete the implementation of the instruction set architecture. The design of the control unit must involve a coordinated definition of both the hardware organization and the microprogram organization. In particular , dividing the microprogram into microroutines, while a
13、t the same time designing the sequencer with which they interact, is a key part of the design. Even the instruction fields and opposed are tied to this coordinated effort. Following the definition of the hardware and microcode organizations, we detail essential parts of the microcode and the microro
14、utines for representative operations. Instruction set architectureFigure 10-1 shows the CISC register set accessible to the programmer. All registers have 16 bits. The register file has eight registers, R0 though R7.R0 is a special register that always supplies the value zero when it is used as a so
15、urce and discards the result when it is used as a destination.In additional to the register file, there is a program counter PC and stack pointer SP. The presence of a stack pointer indicates that a memory stack is a part of the architecture . the final register is the processor status register PSR,
16、 which contains information only in its rightmost the five bits; the remainder of the register is assumed to contain zero. The PSR contains the 2four stored status bit values Z,N,C,and V in positions 3 through 0, respectively. In additional, a stored interrupt enable bit EI appears in position 4. Table 10-1 contains the 42 operations performed by the instructions. Each operation has a mnemonic and a carefully selected oppose. The operations are divided into four groups based on the number of
