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1、1VLSI 复习题型：缩写 5 题 10 分简答 12 题 60 分计算 3 题 30 分缩写 英文 中文VLSI Very large scale integration 超大规模集成VTC Voltage transfer characteristic 电压传输特性PT Pass-Transistor 传输管TG Transmission Gate 传输门CPL/DPL Differential Pass-transistor Logic 差分传输管逻辑MS Master-Slave 主从ET Edge-Triggered 边沿触发CMOS Complementary metal oxid
2、e semiconductor 互补型金属氧化物半导体管NoC On-Chip Network 片上网络SoC System on Chip 片上系统IP Intellectual Property 专利GA Gate Array 门阵列FPGA Field-Programmable Gate Array 现场可编程门阵列PLA Programmable Logic Array 可编程逻辑阵列PLD Programmable Logic Device 可编程逻辑器件PAL Programmable Array Logic Device 可编程阵列逻辑器件LUT Look-up Table 查表
3、FAMOS Floating-gate transistor(metal oxide semiconductor) 浮栅晶体管S/DRAM Static/Dynamic Random Access Memory 静/动态可读写存储器RWM Read-write memory 读写存储器ATD Address Transition Detection 地址翻转探测DFT Design-for-test 可侧性设计DUT Device under test 被测器件BIST Built in self test 内建自测试EDA Electronic Design Automation 电子设计自
4、动化TSPCR True Single-Phase Clocked Tegister 真单相钟控寄存器Chapter 011. How to evaluate performance Cost Reliability Speed (delay, operating frequency) Power dissipation22. Regenerative property3. Delay :Chapter 021. Inverter layout2. Photolithography process1) Oxidation layering(氧化层)2) Pthotoresist coating
5、（涂光刻胶）3) Stepper exposure（光刻机曝光）4) Photoresist development and bake(光刻胶的显影和烘干)5) Acid etching（酸刻蚀）6) Spin, rinse, and dry（旋转，清洗和干燥）7) Various process steps：Ion implantation（离子注入）Plasma etching（等离子刻蚀）Metal deposition（金属沉淀）8) Photoresist removal( or ashing) 去除光刻胶（即“沙洗 ”）Chapter 031. Linear/ Saturation
6、 mode2. Long channel vs short channel33. Capacitances= structure capacitances+channel capacitances+MOS diffusion capacitances4. Resistance=MOS sructure resistance+source and drain resistance+cantact resistance+wiring resistanceWith silicidation R 方块 is reduced to the range 1 to 4 /方块（source and drai
7、n resistance）Chapter 041. Cwire = Cpp + Cfringe + Cinterwire2. Dealing with resistance:1) Use better interconnect materials2) More interconnect layers43. RC Mode Lumped RC model total wire resistance is lumped into a single R and total capacitance into a single C good for short wires; pessimistic an
8、d inaccurate for long wires Distributed RC model circuit parasitics are distributed along the length, L, of the wire4. DelayDelay of a wire is a quadratic function of its length, LThe delay is 1/2 of that predicted (by the lumped model)5. Reflection coefficient【画传输图（or 波形） ，计算题】Chapter 051. VM (W/L)
9、p/(W/L)nIncreasing the width of the PMOS moves VM towards VDD, Increasing the width of the NMOS moves VM towards GND.2. Delay3. Power in CMOS1. Dynamic power consumption: charging and discharging capacitors; Not a function of transistor sizes;Need to reduce CL,Vdd,and f to reduce power.2. Short circ
10、uit currents: short circuit path supply rails during switching; Keep the input and output rise/fall times the same;If VddVtn+|Vtp|,then short-circuit power can be eliminated.3. Leakage: leaking diodes and transistors4. Technology scaling modelsFull scalingFixed voltage scalingGeneral scalingChapter
11、061. Static CMOS- output connected to either Vdd or GND via a low-resistance path High noise margins Low output impedance, high input impedance No steady state path between Vdd and GND Delay is a function of load capacitance and transistor resistanceDynamic CMOS-relies on temporary storage of signal
12、 values on capacitance of high-5impedance circuit nodes. Simpler, faster gates Increased sensitivity to noise2. Static vs dynamic circuit In static circuit at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.-fan-in of N requires 2N d
13、evices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes-requires only N+2 transistors-takes a sequence of precharge and conditional evaluation phases to realize logic functions. conditions on output1) once the optput of a dynamic gate is disc
14、harged, it cannot be charged again until the next precharge opreation.2) Inputs to the gate can make at most one transition during evaluation.3) Output can be in the high impedance state during and after evaluation(PDN off), state is stored in CL. Properties of Dynamic Gates1) Logic function is impl
15、emented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) should be smaller in area than static complementary CMOS2) Full swing outputs (VOL = GND and VOH = VDD)3) Nonratioed-sizing of the devices is not important for proper functioning (only for performance)4)
16、 Faster switching speeds5) Power dissipation should be better- consumes only dynamic power no short circuit power consumption since the pull- up path is not on when evaluating- lower CL-both Cint(since there are fewer transistors connected to the drain output) and Cext (since there the output load is one per connected gate, not two)- by construction can have at most one transition per cycle no glitching6) Needs a percharge clock3. Co
