《《EDA技术》习题(解答)5》由会员分享，可在线阅读，更多相关《《EDA技术》习题(解答)5（9页珍藏版）》请在金锄头文库上搜索。
1、EDA 技术习题5 习 题5-1 归纳利用 Quartus II 进行 VHDL 文本输入设计的流程：从文件输入一直到 SignalTap II 测试。P95P115答：1 建立工作库文件夹和编辑设计文件；2 创建工程；3 编译前设置；4 全程编译；5 时序仿真；6 引脚锁定；7 配置文件下载；8 打开 SignalTap II 编辑窗口；9 调入 SignalTap II 的待测信号；10 SignalTap II 参数设置；11 SignalTap II 参数设置文件存盘；12 带有 SignalTap II 测试信息的编译下载； 13 启动 SignalTap II 进行采样与分析；14
2、 SignalTap II 的其他设置和控制方法。5-2 由图 5-40 和图 5-41，详细说明工程设计 CNT10 的硬件工作情况。P114P115答：图 5-40 给出工程设计 CNT10 的十进制计数工作情况；当计数 CQ 或 CQI 到 9 时,计数进位 COUT 输出正脉冲。 图 5-41 给出工程设计 CNT10 的十进制计数和内部计数节点CQI 计数线性递增的信号波形的工作情况。5-3 如何为设计中的 SignalTap II 加入独立采样时钟?试给出完整的程序和对它的实测结果。P115答：为 SignalTap II 提供独立时钟的方法是在顶层文件的实体中增加一个时钟输入端口
3、，如语句:LOGC_CLK:IN STD_LOGIC;在此实体中不必对其功能和连接具体定义，而在SignalTap II 的参数设置中则可以选择 LOGC_CLK 为采样时钟。5-4 参考 QuartusII 的 Help，详细说明 Assignments 菜单中 Settings 对话框的功能。(1)说明其中的 Timing Requirements&Qptions 的功能、他用方法和检测途经。Specifying Timing Requirements and Options (Classic Timing Analyzer)You can specify timing requireme
4、nts for Classic timing analysis that help you achieve the desired speed performance and other timing characteristics for the entire project, for specific design entities, or for individual clocks, nodes, and pins. When you specify either project-wide or individual timing requirements, the Fitter opt
5、imizes the placement of logic in the device in order to meet your timing goals. You can use the Timing wizard or the Timing Analysis Settings command to easily specify all project-wide timing requirements, or you can use the Assignment Editor to assign individual clock or I/O timing requirements to
6、specific entities, nodes, and pins, or to all valid nodes included in a wildcard or assignment group assignment.To specify project-wide timing requirements: 1. On the Assignments menu, click Settings.2. In the Category list, select Timing Analysis Settings. 3. To specify project-wide tSU, tH, tCO, a
7、nd/or tPD timing requirements, specify values under Delay requirements.4. To specify project-wide minimum delay requirements, specify options under Minimum delay requirements.5. Under Clock Settings, select Default required fmax.6. In the Default required fmax box, type the value of the required fMA
8、X and select a time unit from the list.7. If you want to specify options for cutting or reporting certain types of timing paths globally, enabling recovery/removal analysis, enabling clock latency, and reporting unconstrained timing paths, follow these steps: Click OK.To specify clock settings: 1. O
9、n the Assignments menu, click Settings.2. In the Category list, select Timing Analysis Settings. 3. Under Clock Settings, click Individual Clocks. 4. Click New.5. In the New Clock Settings dialog box, type a name for the new clock settings in the Clock settings name box.6. To assign the clock settin
10、gs to a clock signal in the design, type a clock node name in the Applies to node box, or click Browse. to select a node name using the Node Finder.7. If you want to specify timing requirements for an absolute clock, follow these steps: If you have already specified timing requirements for an absolu
11、te clock, and you want to specify timing requirements for a derived clock, follow these steps: In the New Clock Settings dialog box, click OK.10. In the Individual Clocks dialog box, click OK.11. In the Settings dialog box, click OK.To specify individual timing requirements: 1. On the Assignments me
12、nu, click Assignment Editor.2. In the Category bar, select Timing to indicate the category of assignment you wish to make.3. In the spreadsheet, select the To cell and perform one of the following steps: Type a node name and/or wildcard that identifies the destination node(s) you want to assign. Dou
13、ble-click the To cell and click Node Finder to use the Node Finder to enter a node name. Double-click the To cell, click the arrow that appears on the right side of the cell, and click Select Assignment Group to enter an existing assignment group name.4. To specify an assignment source, repeat step
14、3 to specify the source name in the From cell.5. In the spreadsheet, double-click the Assignment Name cell and select the timing assignment you wish to make.6. For assignments that require a value, double-click the Value cell and type or select the appropriate assignment value. To specify timing ana
15、lysis reporting restrictions: 1. On the Assignments menu, click Settings.2. In the Category list, double-click Timing Analysis Settings.3. Click Timing Analyzer Reporting. 4. To specify the range of timing analysis information reported, specify one or more options in the Timing Analyzer Reporting pa
16、ge.5. Click OK.(2)说明其中的 Compilation Process 的功能和使用方法。Compilation Process Settings Page (Settings Dialog Box)Allows you to direct the Compiler to use smart compilation, save synthesis results for the current designs top-level entity, disable the OpenCore Plus hardware evaluation feature, or export version-compatible database files. You can also control the amount of disk space used for compilation.Use Smart compilation: Preserve fewer node names to save disk s
