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1、Wuxi Microelectronics Institute无锡微电子中心第二研究室( 中微晶园有限公司 )设 计 规 则（工艺接口文件之一）Tel:0510-5807123-2205 Fax:0510-5807123-3515Wuxi Microelectronics Institute1.2um Si-Gate CMOS Process Version # : C12NWSPDM01Page 21.2um Si-Gate CMOS Single Poly Double Metal ProcessOutline: Process Features Masking Layers and Pr
2、ocess Bias Schematic of Process Flow Design Rules PCM Specification SPICE ParametersIssued by ： Xiao zhiqiangChecked by ： Gao fengApproved by ： Xu zhengWuxi Microelectronics Institute1.2um Si-Gate CMOS Process Version # : C12NWSPDM01Page 31.2um Si-Gate CMOS ProcessWafer Start P Substrate 14-25 ohm-c
3、mWell Formation Nwell Xj = 3.0umIsolation Formation Locos: Birds Beak = 0.3um/sideTransistor Gox = 25nmN-Channel NLDD, P-Channel PLDDXj N+ = 0.25umXj P+ = 0.35umILD TEOS/BPTEOS 200nm/600nm Metal1 AlSiCu 550nmIMD TEOS/EB/TEOS total:1200nmMetal2 AlSiCu 1100nmPassivation TEOS/PESIN 200nm/1000nmWuxi Mic
4、roelectronics Institute1.2um Si-Gate CMOS Process Version # : C12NWSPDM01Page 41. 2um Si Gate CMOS SPDM Masking LayersNo. Process Sequence Mask Name Digitized Tone1. Nwell 11 Clean2. Island 20 Dark3. N-ch Field 31 Dark4. Poly 51 Dark5. N+ S/D 61 Clean6. P+ S/D 62 Clean7. Contact 71 Clean8. Metal1 81
5、 Dark9. Via 72 Clean10. Metal2 82 Dark11. PAD 90 CleanWuxi Microelectronics Institute1.2um Si-Gate CMOS Process Version # : C12NWSPDM01Page 51.2um Si Gate CMOS SPDM Process BiasNo. Process Sequence Bias/Side1 Nwell 0.0um2 Island -0.3um *3 N-ch Field 0.0um4 Poly 0.0um5 N+ S/D 0.0um6 P+ S/D 0.0um7 Con
6、tact 0.05um8 Metal1 -0.1um9 Via 0.05um10 Metal2 -0.1 um11 PAD 0.0um* Defined on Birds Beak Wuxi Microelectronics Institute1.2um Si-Gate CMOS Process Version # : C12NWSPDM01Page 61.2um Si-Gate CMOS Design Rule注：以下尺寸皆为最终尺寸Layer 11 N-well Dimension11.1 N-well to N-well spacing (same potential) 2.211.2
7、N-well to N-well spacing (different potential) 7.011.3 Minimum N-well width 4.011.4 N+ island to N-well edge (Inside P-well) 3.511.5 P+ island to N-well edge (inside N-well) 3.511.6 N+ well tab to P-well edge 1.011.7 P+ well tab to P-well edge 1.2Layer 12 P-well Generate from p-wellLayer 20 Island D
8、imension20.1 Minimum island width 1.220.2 Minimum island spacing 1.820.3 Island to die boundary 20.0Layer 31 Field implant Generate from n-wellWuxi Microelectronics Institute1.2um Si-Gate CMOS Process Version # : C12NWSPDM01Page 71.2um Si-Gate CMOS Design RuleLayer 51 Poly Dimension51.1 Minimum poly
9、 width 1.251.2 Minimum poly spacing 1.251.3 Minimum poly to related island edge 1.651.4 Minimum poly to unrelated island edge 0.551.5 Minimum poly extension beyond island 1.2Layer 61 N Island Dimension61.1 Minimum N island width 1.261.2 Minimum N island spacing 1.861.3 Minimum N island spacing to P
10、island 2.061.4 Minimum poly space to butting island edge 1.461.5 Minimum space between butting island edge to N island edge 1.4Note: N+S/D implant is generated form N island mask by sizing up, care need to be takento make sure the minimum space on reticle is not less than 1.0um, minimum width on ret
11、icle is not less than 1.5um.1.2um Si-Gate CMOS Design Rule (continue) Wuxi Microelectronics Institute1.2um Si-Gate CMOS Process Version # : C12NWSPDM01Page 8Layer 62 P Island Dimension62.1 Minimum P island width 1.262.2 Minimum P island spacing 1.862.3 Minimum P island spacing to N island 2.061.4 Mi
12、nimum poly space to butting island edge 1.461.5 Minimum space between butting island edge to P island edge 1.4Note: P+S/D implant is generated form P island mask by sizing up, care need to be takento make sure the minimum space on reticle is not less than 1.0um, minimum width on reticle is not less
13、than 1.5um.Layer 71 Contact Dimension71.1 Contact size (One size) 1.271.2 Minimum poly enclosure of contact 0.971.3 Minimum contact to poly spacing 1.071.5 Minimum island enclosure of contact 1.071.6 Minimum contact to contact spacing 1.271.7 Minimum poly contact to any-island 1.271.8 Island contact
14、 to unrelated island space 2.071.9 Contact not allowed on poly on top of gate oxideWuxi Microelectronics Institute1.2um Si-Gate CMOS Process Version # : C12NWSPDM01Page 91.2um Si-Gate CMOS Design Rule (continue)Layer81 Metal 1 Dimension81.1 Minimum metal 1 width 1.781.2 Minimum metal 1 space 1.581.3
15、 Minimum metal 1 enclosure of contact 1.081.4 Minimum metal 1 enclosure of metal via 1.081.5 Minimum metal 1 to die boundary 20.0Layer 72 Metal via Dimension72.1 Metal via size (One size except for passivation pad) 1.272.2 Minimum metal via to contact space (Metal via not allowed on top of contact)1.472.3 Minimum metal via to metal via space 1.472.4 Metal via to edge of poly (Can be enclosed by poly
