《硕士学位论文QAM信号全数字解调技术》由会员分享，可在线阅读，更多相关《硕士学位论文QAM信号全数字解调技术（115页珍藏版）》请在金锄头文库上搜索。
1、硕 士 学 位 论 文题 目: QAM 信号全数字解调技术 研 究 生 郑 国 专 业 信 号 与 信 息 处 理 指导教师 张 公 礼 教 授 完成日期 2004 年 12 月 杭州电子科技大学硕士学位论文QAM 信号全数字解调技术研 究 生： 郑 国指导教师： 张 公 礼 教授2004 年 12 月Dissertation Submitted to Hangzhou Dianzi Universityfor the Degree of MasterTechnology of the All-Digital Demodulation for QAM SignalCandidate: Zhen
2、g GuoSupervisor: Prof. Zhang GongliDecember，2004杭州电子科技大学硕士学位论文I摘 要在通信业务日益增长、载波频段日益拥挤的今天，频谱利用率是一个主要矛盾。正交幅度调制（QAM）是一种频谱利用率很高、实现较为方便的载波传输方式，它以其高效的频谱利用率在当今众多的调制方式中具有很强的竞争力。QAM调制方式有效缓解了传输网络的带宽矛盾。一般数字调制方式一般只有一个信号参量携带调制信息，而QAM调制的调制信号幅度和相位都携带信息，对于M进制QAM中随M值的增大，所携带的信息量也随着增加，大大提高了信道的利用率，因此QAM调制方式被广泛的应用于了传输领域。
3、此外QAM 信号的码间距比MASK, MPSK的要大，所以在提高频带的利用率基础上，对误码率的影响不大，也是它得到广泛应用的一个原因。因此，QAM同时具有带宽利用率和误码率两大优点。全数字解调克服了由于 QAM 信号相位差较小等引起的传统接收机的困难，是QAM 信号解调中的重要研究方向。本文重点研究 QAM 信号的全数字解调技术。介绍了多进制正交幅度调制（MQAM）信号的基本原理和特点。组建了一个全数字接收机结构，并介绍了一种硬件实现方法。本文对多进制正交幅度调制（MQAM）信号的检测估计理论及性能分析方法进行了研究，给出了适合于实际中应用的评价标准修正克拉美罗限（MCRB）和渐近克拉美罗限（
4、ACRB ） 。这种科学的性能评价体系，为后面的算法性能改进提供了理论根据，也为进一步的算法研究打下了基础。本文研究了 QAM 信号的数字下变频技术。介绍了专用可编程数字下变频器件HSP50214B，并说明了这种器件的一般设计方法。利用可编程逻辑器件 CPLD 通过硬件描述语言 VHDL 编程，完成了基于专用下变频器件 HSP50214B 的对一种实际的 256QAM 信号的下变频。算法研究是本文的重点所在。在载波同步方面的频偏估计问题，通过对现有算法的研究，提出了一种新的载波频偏捕获方法。这种新的频偏算法即保证了频偏捕获范围，又提高了捕获精度，有效的解决了传统算法中两者不能兼顾的问题，可用于
5、 QAM 系统以及 MPSK 系统中的频偏估计。在相位估计算法中，完成了一系列利用接收信号统计信息的相位估计算法的渐近误差性能分析，并通过比较，得到估计性能较好的相位估计算法。在符号定时估计方面，研究了两种适合不同采样率的定时估计算法，并进行了重要改进。文章中对以上所有算法进行了仿真，得到大量可靠的仿真数据。最后，对本文研究成果进行总结并提出问题。杭州电子科技大学硕士学位论文II关键词：非数据辅助，同步，多进制正交幅度调制，全数字接收杭州电子科技大学硕士学位论文IIIABSTRACTWith the rapid development of the electronics and comput
6、er science, particularly the improvement of the operation speed in digital signal process (DSP) chip, the digital signal process technique appears to be an important problem, and defined the concept of all digital receiver and the software radio. The goal of the all digital receiver included the ope
7、ning architecture and the full-scale programmable, it is easily to update the communication function by altered the configuration of the hardware. The characteristic of this all digital receiver is the local oscillator carrier and sampling clock run at fixed frequencies. DSP and VLSI chip mainly est
8、imates and revises the error signals. In contrast to conventional receiver, all-digital receiver does not require the feedback of signals to the analog part, so all-digital receiver overcomes difficulties in phase lock loop design. No feedback enhances not only stability and compatibility but also c
9、omplexity, so choosing algorithms is a main topic of all-digital receiver ,which is effectible, fleetly convergent and easy to realize by DSP and VLSI chip。The goal of this paper is to research the several key technologies of all-digital demodulation for QAM signal. The paper propose a all digital r
10、eceiver architecture . And give a hardware circuit of IF digital receiver designed by the thesis in order to realize the real-time processing of the received intermediate frequency signals and make a concrete analysis of the signal characteristic and functions of each module. In synchronization incl
11、uded digital frequency conversion technique, carrier synchronization and symbol timing synchronization. In this paper, introduce feedforward nondata-aided(NDA) estimators and a all digital receiver architecture. Firstly, the paper introduces the technologies of quadrature amplitude modulation and th
12、e theoretics of estimate. In order to analyze system performance and design appropriate equipment, we present the Cramer-Rao bound(CRB) related to estimating the synchronization parameters, a modified CRB (MCRB) and a asymptotic CRB (ACRB) have been derived. Based this standard, a rigorous and thoro
13、ugh performance analysis was setups for the existing blind estimators.The paper presents the Block Diagram and the Functional Description of the HSP50214B.The output mode and microprocessor was appicacted based on the requirement of the 256QAM signal in wireless LAN. The parameter of HSP50214B was c
14、onfigurated.The PDC configuration is realized by using VHDL program by the logical 杭州电子科技大学硕士学位论文IVdevice CPLD. The PDC configuration process indicates the general method of the HSP50214B application.The paper introduces several key technologies in all-digital receiver, including estimating and revi
15、sing timing phase offset ,carrier frequency offset and carrier phase offset。 The aim is bringing forward the digital signal processing algorithm suited for all-digital receiver implemented by DSP. The author compared some carrier synchronization algorithms of all-digital receiver, proposed a new arc
16、hitecture for M-QAM signals. This approach exhibits more robustness and larger acquisition range than conventional ones. In the carrier phase estimation, the paper performed the thorough performance analysis of a class of blind algorithms. By analysis, proposed a computationally simple blind carrier phase estimators with guaranteed convergence and good statistical properties. In symbol e
