《2014-2015年(二)《数字逻辑设计与应用》期中试卷参考解答》由会员分享，可在线阅读，更多相关《2014-2015年(二)《数字逻辑设计与应用》期中试卷参考解答（7页珍藏版）》请在金锄头文库上搜索。
1、电子科技大学2014 - 2015 学年第 二 学期期 中 考试卷课程名称：数字逻辑设计及应用 考试形式：闭卷 考试日期：2015年5月10日 考试时长：120分钟课程成绩构成：平时 30/20 %， 期中 30/20 %， 小班讨论 0/20 %， 期末 40 %本试卷试题由_VII_部分构成，共_6_页。题号IIIIIIIVVVIVII合计得分得 分I. Please fill out the correct answers in the brackets “( )” . ( 2 X 20 = 40 )1. 510.5 10 = ( .1 )2 = ( 1FE.8 ) 16 2. (201
2、5)10 =( 10101 )8421BCD =( 01000 ) Excess-33. If Xs signed-magnitude representation XSM is , then (2X)s 8-bit twos complement representation is ( ), and (-X/2)s 8-bit twos complement representation is ( ). 4. If a logic function is F=(A,B,C)(1,2,3,6), its complement expression is F=(A,B,C)( ) (0,4,5,
3、7), and its dual expression is FD=(A,B,C)( ).(0,2,3,7)5. For CMOS inverters, can different outputs of common CMOS inverters be connected together? Yes or No ( No ); Three-state inverters have three-state outputs, which are HIGH、LOW and (Hi-Z ). Can different outputs of three-state inverters be conne
4、cted together? Yes or No (Yes).6. Given a binary number X=, its corresponding Gray code is ( ).7. If X twos-complement =0111 00112, Y twos-complement =1001 11002, then X-Y twos-complement=（ ），whether overflow occurs? Yes or No ( Yes ).8. Given 126 different states, it requires at least (7 ) binary b
5、its to represent them.9. For CMOS NOR gates, their unused inputs should connect to (0 ) state.10. From Table 1 below, if 74HC devices drive 74LS devices, in HIGH state , DC noise margin VNH is ( 1.84 ), Fan-out NH is ( 200 ); in LOW state , DC noise margin VNL is ( 0.47 ), Fan-out NL is ( 10 ).Table
6、 1 FamilyDescriptionSymbol74LS74HCLOW-level input voltage (V)VILmax0.81.35LOW-level output voltage (V)VOLmax0.50.33HIGH-level input voltage (V)VIHmin2.03.85HIGH-level output voltage (V)VOHmin2.73.84LOW-level input current (uA)IILmax-4001LOW-level output current (mA)IOLmax84HIGH-level input current (
7、uA)IIHmax20-1HIGH-level output current (mA)IOHmax-0.4-4得 分II. Choose the correct answer and fill the item number in the brackets. (Single selection for question 18, Multi-selection for 910, 2 X 10=20 )1. For logic function F=AB+ABCD+ABDEF+ABCE , its minimal sum is ( C )A. F=AB+CD+DEF+BCE B. F=AB+CD+
8、EF+CE C. F=AB+BCE D. F=AB 2. Given a circuit design, its output expression with positive logic is F=AB+CD+EF, then its output expression with negative logic is (C)A. F=A+BC+DE+F B. F=(AB)(CD)(EF)C. F=A+BC+D(E+F) D. F=AB+CD+EF3. For the priority encoder 74X148, its inputs are: I0-L, I1-L, I2-L, I3-L,
9、 I4-L, I5-L, I6-L, I7-L，outputs are Y2-L,Y1-L,Y0-L. The inputs and outputs are all active-low. When active-low enable input EN_L=0, I1-L = I5-L = I4-L =0, and any other inputs are all 1, then Y2-L, Y1-L, Y0-L is ( B ). A. 110 B. 010 C. 001 D. 101 4. Except enable lines, an 8-1 multiplexer should hav
10、e (C) control/select lines.A. 1 B. 2 C. 3 D. 4 5. The truth table of a circuit is shown in Table 2, the logic expression of this circuit is ( D ).A. F=A+B B. F=S+A+B C. F=SA+SB D. F=SA+SB Table 2SABF000000110100011110001010110111116. In one number system ,if an arithmetic operation 41=5 is correct,
11、its radix is ( B )A. 5 B. 6 C. 7D. 87. In figure 1, the output logic function is (B)A) Y=(AB)+(CDE)B)Y=(AB)(CDE)VccAAABACADAEAYAFigure 1C) Y=(A+B+C+D+E)D)Y=(ABCDE)8. If the minimal sum of a logic function is same as canonical sum, it may have (D).A. static-0 hazard B. static-1 hazardC. both static-0
12、 hazard and static-1 hazard D. neither static-0 hazard nor static-1 hazard9. In two-level AND-OR circuit design, our minimization is aimed to (BC)A. minimize the inputs of OR gates B. minimize the number of AND gatesC. minimize the inputs of AND gates D. shorten the signal path from input to output1
13、0. Methods that are (ABCD) can be used to describe combinational circuitsA. sum-of-products B. product-of-sumsC. truth tableD. timing diagramIII. Combinational Circuit Analysis And Design: 401.Given F(W,X,Y,Z)=W/Y/Z/+W/X/Z+WXY/Z+YZ, there are also dont-cares defined as d(9,12,14). Simplify the logic function F(A,B,C,D) into the minimal-product using Karnaugh map, and write out NOR-NOR logic expression of the minimal-product. (8)参考评分标准：1.填写F的卡诺图正确4分 2.化简的表达式正确2分Fminimal-product (W,X,Y,
