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1、Quartus II Software Design Series: Timing Analysis,2,Objectives,Build SDC files for constraining PLD designs Verify timing on simple use wildcards in targets or command),TimeQuest main: Constraints Create Clock SDC Editor: Edit Insert Constraint Create Clock,24,Name Finder,Clicking on Browse button
2、opens Name Finder allowing you to search netlist for node names (similar to Quartus II Node Finder),Select collection to search,Edit command here or final command to use wildcards,Options available depend on selected collection,25,Name Finder Search Options,All options off Hierarchy levels in Filter
3、 match results except for * * finds all names in all levels of hierarchy in selected collection Ex: * | data* finds names starting with data at second level only Case-insensitive (all collections) Names match Filter ignoring capitalization Hierarchical (get_pins; get_cells collections only) Filter m
4、ust be just cell name or in form of | Ex: foo | * finds all pins on cell named foo Ex: * | data* finds all pins starting with data at any level of hierarchy Compatibility mode (get_pins; get_cells collections only) Always searches entire hierarchy Ex: * | data* finds all pins starting with data at a
5、ny level of hierarchy Ex: * | * | data* performs the same search; extra * | not required,26,Creating a Generated Clock,Command: create_generated_clock Options -name -source -master_clock -divide_by -multiply_by -duty_cycle -invert -phase -edges -edge_shift -add,27,create_generated_clock Notes,source
6、: Species the node in design from which generated clock is derived Ex. Placing source before vs. after an inverter would yield different results master_clock: Used if multiple clocks exist at source due to -add option edges: Relates rising/falling edges of generated clock to rising/falling edges of
7、source based on numbered edges -edge_shift: Relates edges based on amount of time shifted (requires -edges),28,Create Generated Clock using GUI,29,Generated Clock Example 1,create_clock period 10 get_ports clk_in create_generated_clock name clk_div source get_pins inst|clk -divide_by 2 get_pins inst
8、|regout,Source pin,Target pin,30,Generated Clock Example 2,clk_in,1,2,3,4,5,6,7,8,pulse_clk_out,master edges,create_clock period 10 get_ports clk_in create_generated_clock name pulse_clk_out -source clk_in edges 1 4 5 get_pins pulse_logic|out # Master edges are numbered 1. In the edge list, the firs
9、t # number corresponds to the first rising edge of the generated # clock. The second number is the first falling edge. The third # number is the second rising edge. Thus, a clock is created that # is half the period of the source with a 75% duty cycle.,31,Generated Clock Example 3,clk_in,1,2,3,4,5,6
10、,7,8,pulse_clk_out,master edges,create_clock period 10 get_ports clk_in create_generated_clock name pulse_clk_out -source clk_in edges 1 4 5 -edge_shift 2.5 2.5 0 get_pins pulse_logic|out # Same as example 2 except -edge_shift shifts each edge indicated # amount of time,32,PLL Clocks (Altera SDC Ext
11、ension),Command: derive_pll_clocks -use_tan_name: names clock after design net name from Classic timing analyzer settings instead of the default PLL output SDC pin name -create_base_clocks: generates create_clock constraint(s) for PLL input clocks Create generated clocks on all PLL outputs Based on
12、input clock must be entered in SDC manually,33,derive_pll_clocks Example,create_clock period 10.0 get_ports in_clk derive_pll_clocks # or simply: derive_pll_clocks create_base_clocks # Note the clock names for # the generated clocks # will be the names of # the PLL output pins,create_clock period 10
13、.0 get_ports in_clk create_generated_clock name c100 source get_pins inst|altpll_component|pll|inclk0 -divide_by 1 get_pins inst|altpll_component|pll|clk0 create_generated_clock name c200 source get_pins inst|altpll_component|pll|inclk0 -multiply_by 2 get_pins inst|altpll_component|pll|clk1 create_g
14、enerated_clock name c200_shift source get_pins inst|altpll_component|pll|inclk0 -multiply_by 2 -phase 90 get_pins inst|altpll_component|pll|clk2,Using generated clock commands,Using derive pll command,34,Automatic Clock Detection add options manually,44,Clock Uncertainty (GUI),45,Automatically Deriv
15、e Uncertainty,Command: derive_clock_uncertainty Automatically derive clock uncertainties in supported devices Cyclone III, Stratix II, HardCopy II, Stratix III, and new devices Uncertainties created manually with set_clock_uncertainty have higher precedence Options -overwrite: overwrites any existin
16、g uncertainty constraints -add: adds derived uncertainties to existing constraints SDC extension expanded with write_sdc -expand Not in GUI,46,Types of Derived Uncertainties,Intra-clock transfers Transfers within a single clock domain within FPGA Inter-clock transfers Transfers between different clock domains within FPGA I/O interface clock transfers Transfers between an I/O port and internal design registers Requires creation of virtual clock as reference clock for set_input_del
