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1、附录9：整体实物图附录10：英文原文Memory Subsystem Organization and InterfacingIn this section we examine the construction and functions of the memory subsystem of a computer. We review the different types of physical memory and the internal organization of their chips. We discuss the construction of the memory sub
2、system, as well as multibyte word organizations and advanced memory organizations.1 Types of MemoryThere are two types of memory chips ; read only memory(ROM) and random access memory(RAM). Read Only Memory(ROM) chips are designed for applications in which data is only read. (This data can include p
3、rogram instructions.)These chips are programmed with data by an external programming unit before they are added to the computer system. Once this is done, the data usually does not change. A ROM chip always retains its data, even when power to the chip is turned off. As an example, an embedded contr
4、oller for a microwave oven might continuously run one program that does not change. That program would be stored in a ROM.Random Access Memory (RAM), also called read/write memory, can be used to store data that change. This is the type of memory referred to as X MB of memory in ads for PCs. Unlike
5、ROM,RAM chips lose their data once power is shut off. Many computer system, including personal computers, include both ROM and RAM.2 Internal Chip OrganizationThe internal organizations of ROM and RAM chips are similar. To illustrate the simplest organization, a linear organization, consider an 8x2
6、ROM chip. For simplicity, programming components are not shown。 This chip has three address inputs and two data outputs, and 16 bits of internal storage arranged as eight 2-bit locations.The three address bits are decoded to select one of the eight locations, but only if the chip enable is active. I
7、f CE=0, the decoder id disabled and no location is selected. The tri-state buffers for that locations cells are enabled, allowing data to pass to the output buffers. If both CE and OE set to 1, these buffers are enabled and the data is output from the chip; otherwise the outputs are tri-stated.As th
8、e number of the locations increases, the size of the address decoder needed in a linear organization becomes prohibitively large. To remedy this problem, the memory chip can be designed using multiple dimensions of decoding.In large memory chips, this savings can be significant. Consider a 4096x1 ch
9、ip. The linear organization will require a 12 to 4096 decoder, the size of which is proportional to the number of outputs. (The size of an n to decoder id thus said to be O ().) If the chip is organized as a 64x64 two dimensional array instead, it will have two 6 to 64 decoders: one to select one of
10、 the 64 rows and the other to select one of the 64cells within the row. The size of the decoders is proportional to 2x64,or O (2x)=O (). For this chip, the two decoders together are about 3 percent of the size of the one large decoder.3 Memory Subsystem ConfigurationIt is very easy to set up a memor
11、y system that consists of a single chip. We simpley connect the address, data, and control signals from their system buses and the job is done. However, most memory systems require more than one chip. Following are some methods for combining memory chips to form a memory subsystem.Two or more chips
12、can be combined to create memory with more bits per location. This is done by connecting the corresponding address and control signals of the chips, and connecting their data pins to different bits of the data bus. For example, two 8x2 chips can be combined to create an 8x4 memory, as shown in Figur
13、e 2-4. Both chips receive the same three address inputs from the bus, as well as the same chip enable and output enable signals. (For now it is only important to know that the signals are the same for both chips; we show the logic to generate these signals shortly.) The data pins of the first chip a
14、re connected to bits 3 and 2 of the data bus, and those of the other chip are connected to bits 1 and 0.Figure 4 An 8x4 memory subsystem constructed from two 8x2 ROM ChipsWhen the CPU reads data, it places the address on the address bus. Both chips read in address bits A2, A1, and Ao and perfonn the
15、ir intemal decoding. If the CE and OE signals are activated, the chips output their data onto the fom bits of the data bus. Since the address and enable signals are the same for both chips, either both chips or neither chip is active at any given time. The computer never has only one of the two acti
16、ve. For this reason, they act just as a single 8x4 chip, at least as far as the CPU is concerned.Instead of creating wider words, chips can be combined to create more words. The same two 8 x2 chips could instead be configured as a 16x2 memory subsystem. This is illustrated in Figure 2-5(a). The upper chip is configured as memory locations 0 to 7 (0000 to OI II) and the lower chip as locations 8 to 15 (IOOO to l l Il). The upper ch
