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1、1,Class Exercise,1、Analyse the logic relationship between the input and output of the circuit below.,2,Answer key,3,CMOS Steady-State Electrical Behavior ( CMOS稳态电气特性） Logic Levels （逻辑电压电平） Noise Margin （噪声容限）,Review of lass class,4,Logic level and noise margin,The input limit : avoid the noise be a
2、mplified!,Review of lass class,5,Circuit Behavior with Resistive Loads （带电阻性负载的电路特性）,保证提供或吸收的电流小于门电路的规定值,Output Behavior Get Worse with a load (负载导致输出特性变坏),Sinking current,Sourcing current,Review of lass class,6,The output voltage is changed When input voltage changed.,The steady state model of CMOS
3、,Review of lass class,7,非理想输入时的电路特性 输入偏离供电轨道，输出电压变坏,Current Spikes and Decoupling Capacitors (电流尖峰和去耦电容器),Review of lass class,8,Specifications for two kind load: CMOS load: uA Analog load: mA,Output current: driving ability,Review of lass class,9,Driving for Analog device,Hold the voltage margin an
4、d current limit,10,Output driven ability,For NAND in Table 3-3: If VOHmin= 3.84 V Then IOHmax=4 mA R 3.84/4 = 0.96 k,Limitation for output current and resistive load.,11,Use NAND2 to drive LED,Fig 3-54 74AC Device : VOLmax = 0.37 V,12,Fan-Out（扇出） 当输出负载大于它的扇出能力时？ 输出特性变差 电流，功耗 ，温度升高 传输延迟、转换时间变长 Unused
5、 Inputs (不用的CMOS输入端如何处理？),Review of lass class,13,EXAMPLE 2 (P107),14,3.6 CMOS Dynamic Electrical Behavior (CMOS动态电气特性),Consider Two Factors: Speed and Power-Consumption (考虑两个方面：速度、功耗),Review of lass class,15,Any device has input and output capacitors !,Dynamic model of CMOS,Review of lass class,16,
6、Transition Time (转换时间),Consider Two Factors (考虑两个因素)： “On” Transistor Resistance ( 晶体管的“导通”电阻 ) Stray Capacitance （寄生电容）,Figure 3-36,Review of lass class,17,电容两端电压不能突变,When working with Real digital circuit, the Transition Time approximately Equals the RC time Constant (在实际电路中可用时间常数近似转换时间),Transitio
7、n Time (转换时间),Review of lass class,18,Propagation Delay (传播延迟),Signal Path: Electical Path from a Particular Input Signal to a Particular Output Signal of a Logic Element . (信号通路：一个特定输入信号到逻辑元件的 特定输出信号所经历的电气通路。),Review of lass class,19,Power Consumption (功率损耗),Static/Quiescent Power Dissipation and D
8、ynamic Power Dissipation (分为：静态功耗、动态功耗),Review of lass class,20,Power Consumption (功率损耗),两个管子瞬间同时导通产生的功耗 PT 对负载电容充、放电所产生的功耗 PL,Source of Dynamic Power Dissipation (动态功耗的来源):,Review of lass class,21,动态功耗的来源： 两个管子瞬间同时导通产生的功耗 PT 对负载电容充、放电所产生的功耗 PL,Power Consumption (功率损耗),Static/Quiescent Power Dissipa
9、tion and Dynamic Power Dissipation (分为：静态功耗、动态功耗),Review of lass class,22,3.7 Other CMOS Input and Output Structures （其他CMOS输入输出结构） (P129),23,Transmission Gates (传输门),When EN = 0，EN_L = 1， Transistor Off, A,B Off (晶体管截止， A、B断开) When EN = 1，EN_L = 0， Transistor On, A,B On (晶体管导通，A、B之间低 阻抗连接) 双向器件 传播延
10、迟非常短,3.7.1 Transmission Gates(传输门),24,3.7.1 Transmission Gates(传输门),Example 1( P129 Figure 3-46),试分析其功能？,25,一般门电路有一个阈值电压，当输入电压从低电平上升到阈值电压或从高电平下降到阈值电压时电路的状态将发生变化。,3.7.2 Schmitt-Trigger Inputs(施密特触发器输入)(P130),阈值电压VTH，从CMOS非门电压传输特性曲线中看出，输出高低电平的过渡区很陡，阈值电压VTH约为VDD/2 .,26,3.7.2 Schmitt-Trigger Inputs(施密特触
11、发器输入)(P130),Use Feedback Internally ( 采用内部反馈，边沿更陡 ),Logic Symbol (逻辑符号)：,27,Schmitt-Trigger Inputs(施密特触发器输入),Hysteresis: Difference Between the Two Thresholds (滞后：两个门限电压之差),Logic Symbol (逻辑符号)：,28,Example 2,29,Applications of Schmitt-Trigger (施密特触发器的应用),波形变换,30,脉冲整形,Applications of Schmitt-Trigger (
12、施密特触发器的应用),Figure 3-47,31,脉冲鉴幅,Applications of Schmitt-Trigger (施密特触发器的应用),32,从传感器得到的矩形脉冲经传输后往往发生波形畸变。当传输线上的电容较大时，波形的上升沿将明显变坏；当传输线较长，而且接收端的阻抗与传输线的阻抗不匹配时，在波形的上升沿和下降沿将产生振荡现象；当其他脉冲信号通过导线间的分布电容或公共电源线叠加到矩形脉冲信号时，信号上将出现附加的噪声。无论出现上述的那一种情况，只要施密特触发器的vT+和vT-设置得合适，都可以通过用施密特触发器整形而得到比较理想的矩形脉冲波形。,Applications of S
13、chmitt-Trigger (施密特触发器的应用),33,3.7.3 Three-State Outputs (三态输出)(P373),When EN=0， C=1, Tp Off (截止) B=1, D=0, Tn Off Hi-Z, High-Impedance /Floating State (高阻态/悬空态）,34,Three-State Outputs (三态输出),When EN=1， C=A , B=0 , D=A Output Controlled by A is Logic Levels: High or Low (由A控制输出为: 逻辑0 或 逻辑1),35,输出电平？
14、造成逻辑混乱,很大的负载电流 同时流过输出级 可使门电路损坏,3.7.4 Open-Drain Outputs (漏极开路输出)(P133),Active Pull-Up ( 有源上拉 ),有源上拉的CMOS器件 其输出端不能直接相连！,36,希望尽量小，减少上升时间 太小则吸收电流太大,应用：驱动LED、线与、 驱动多源总线,Open-Drain Outputs (漏极开路输出),The underscorded diamond,37,Z = Z1 Z2 = (AB) (CD),3.7.7 Wired Logic of Open-Drain Outputs(漏极开路输出的线连逻辑)(P138
15、),Wired AND (线与),38,Use open gate NAND2 to drive,3.7.7 Wired Logic of Open-Drain Outputs(漏极开路输出的线连逻辑)(P138),39,3.9 Low-voltage CMOS Logic and interfacing 低电压CMOS逻辑和接口(P151),为什么使用低电压？ 减小电源电压可以减小动态功耗 更小的尺寸、更高的集成度 3.3 0.3V 2.5 0.5V 1.8 0.15V,40,3.10 Bipolar Logic (双极逻辑)(P156),Diode Transfer Characteris
16、tic (二极管开关特性),Thresholds(门限电压),Breakdown (反向击穿),Leakage Current (漏电流),41,3.10 Bipolar Logic (双极逻辑),Diode Transfer Characteristic (二极管开关特性),Forward Biased (正偏（导通）),Reverse Biased (反偏（截止）),25 ,0.6V,42,Diode Logic (二极管逻辑),02V Low (低电平) 0 ( 逻辑0) 23V Noise Margin (噪声电平） Undefined (未定义) 35V High (高电平) 1 (逻辑1),Diode AND Gate ( 二极管与门 ),3.10 Bipolar Logic (双极逻辑),43,3.10.2 Bipolar Junction Transistors (双极结型晶体管)(P158),截止区 放大区 饱和区,44,Schottky Tra
