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1、1,REVIEW OF LAST CLASS,2,CMOS inverter,常闭,常开,常闭,常开,in,P 沟道,N沟道,3,CMOS 2-input NAND gate,Q2,CMOS inverter,4,PMOS: when G is 0, Switch on; when G is 1, Switch off; NMOS: when G is 1, Switch on; when G is 0, Switch off;,Two types of MOS transistor,5,CMOS inverter (INV),F: get 1 from PMOS, get 0 from NM
2、OS; When X=1, NMOS is on; When X=0, PMOS is on;,6,NAND / NOR,NAND: NMOS serial , PMOS parallel; NOR: NMOS parallel, PMOS serial;,7,NAND / NOR,NAND: NMOS serial ; NOR: NMOS parallel;,8,Output with positive logic,Buffer AND,9,AND-OR-INVERT (COMS AOI )gate,10,AOI / OAI,11,3.4 Electrical Behavior of CMO
3、S Circuits (CMOS电路的电气特性),Logic voltage levels. ( 逻辑电压电平) DC noise margins(直流噪声容限) Fanout.(扇出) Speed, Power consumption(速度、功耗) Noise, Electrostatic discharge(噪声、静电放电) Open-drain outputs. Three-state outputs (漏极开路输出、三态输出),12,3.5.1 Logic Levels and Noise Margins 逻辑电平和噪声容限,13,电压传输特性,14,CMOS逻辑系列（HC）电平规格,
4、VCC0.1V,地0.1V,0.7VCC,0.3VCC,vcc,0,15,直流噪声容限（DC noise margin） 多大的噪声会使最坏输出电压被破坏得不可被输入端识别.,30%VCC,16,17,VIK:输入钳位电压,在输入端和输出端加钳位电路， 使输入和输出不超过不超过规定电压。,18,3.5.2 Circuit Behavior with Resistive Loads (带电阻性负载的电路特性)(P103),19,3.5.2 Circuit Behavior with Resistive Loads(带电阻性负载的电路特性)(P103),a Thvenin equivalent n
5、etwork,20,REMEMBERING THVENIN,Any two-terminal circuit consisting of only voltage sources and resistors can be modeled by a Thvenin equivalent consisting of a single voltage source in series with a single resistor. The Thvenin voltage is the open-circuit voltage of the original circuit, and the Thve
6、nin resistance is the Thvenin voltage divided by the short-circuit current of the original circuit.,21,Example 1 (P104),22,Resistive model for CMOS LOW outputwith resistive load.,23,Resistive model for CMOS HIGH outputwith resistive load.,24,输出为低态时 VOUT = VOLmax 输出端吸收电流 sinking current 能吸收的最大电流 IOLm
7、ax （灌电流）,(P106),Sinking current 吸收电流,25,输出为高态时 VOUT = VOHmin 输出端提供电流 sourcing current 能提供的最大电流 IOHmax （拉电流）,Sourcing current 提供电流,26,VOUT = 0,VIN = 1,VOUT = 1,VIN = 0,输出为低态时， 估计吸收电流：,输出为高态时， 估计提供电流：,27,EXAMPLE 2 (P107),28,3.5.3 Circuit Behavior with Nonideal Inputs (P108),29,3.5.3 Circuit Behavior w
8、ith Nonideal Inputs非理想输入时的电路特性,输出电压变坏（有电阻性负载时更差） 更糟糕的是：Iwasted ， Pwasted ,30,Example 3 (P110),31,3.5.4 Fanout (P111),32,3.5.4 Fanout （扇出）,The fanout of a logic gate is the number of inputs that the gate can drive without exceeding its worst-case loading specifications. The fanout depends not only on
9、 the characteristics of the output, but also on the inputs that it is driving. Fanout must be examined for both possible output states, HIGH and LOW. 在不超出其最坏情况负载规格的条件下， 一个逻辑门能驱动的输入端个数。 扇出需考虑输出高电平和低电平两种状态 总扇出min（高态扇出，低态扇出） 直流扇出 和 交流扇出,33,EXAMPLE 3 (P111),IImax for an HC-series CMOS input in any state
10、 is 1 A . The LOW-state fanout for an HC-series output driving HC-series inputs is 20.,IImax for an HC-series CMOS input in any state is 1 A . The HIGH-state fanout for an HC-series output driving HC-series inputs is 20.,34,EXAMPLE 4,the fanout of an HC-series output driving HC-series inputs at TTL
11、levels is 4000.,直流扇出,35,3.5.5 Effects of Loading(负载效应),输出负载大于它的扇出能力时（P111） In the LOW state, the output voltage (VOL) may increase beyond VOLmax. In the HIGH state, the output voltage (VOH) may fall below VOHmin.输出电压变差 Propagation delay to the output may increase beyond specifications. Output rise a
12、nd fall times may increase beyond their specifications.传输延迟和转换时间变长 The operating temperature of the device may increase, thereby reducing the reliability of the device and eventually causing device failure. 温度可能升高，可靠性降低，器件失效.,36,3.5.6 Unused Inputs(不用的CMOS输入端),不用的CMOS输入端绝对不能悬空,增加了驱动信号的电容负载，使操作变慢,37,
13、3.6 CMOS Dynamic Electrical Behavior (P114),38,3.6 CMOS Dynamic Electrical Behavior CMOS动态电气特性,考虑两个方面： 速度 功耗,39,3.6 CMOS Dynamic Electrical Behavior (CMOS动态电气特性),CMOS器件的速度和功耗在很大程度上取决于器件及其负载的动态特性。 速度取决于两个特性： transition time（转换时间） propagation delay（传播延迟）,逻辑电路的输出从一种状态变为另一种状态所需的时间,从输入信号变化到产生输出信号变化所需的时间,
14、40,3.6.1 Transition Time (转换时间),rise time(上升时间) tr fall time(下降时间) tf the “on” transistor resistance (晶体管的“导通”电阻) stray capacitance(寄生电容),电容两端电压不能突变,在实际电路中 可用时间常数 近似转换时间,P115 Figure 3-36,41,Example 4 (P117),estimates of 10 ns for fall time .,42,EXAMPLE 5 (P117),estimates of 20 ns for rise time .,43,
15、3.6.2 Propagation Delay(传播延迟),P83 图3-42,信号通路：一个特定输入信号到逻辑元件的 特定输出信号所经历的电气通路。,44,3.6.2 Propagation Delay(传播延迟),信号通路：一个特定输入信号到逻辑元件的 特定输出信号所经历的电气通路。,45,3.6.3 Power Consumption(功率损耗),static power dissipation（静态功耗） dynamic power dissipation（动态功耗） 两个管子瞬间同时导通产生的功耗 PT 对负载电容充、放电所产生的功耗 PL,46,(P 176-179) 3.23 3.27 (b) 计算扇出 3.49 (a) (b) 计算直流噪声容限 3.56 (a) 选做 3.61,Please hand your home work on Next Monday!,HOMEWORK,
