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1、1,Figure 81 A 2-bit asynchronous binary counter. Open to verify operation.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,2,Figure 82 Timing diagram for the counter of Figure 81. As in previous chapters, outpu
2、t waveforms are shown in green.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,3,Figure 83 Three-bit asynchronous binary counter and its timing diagram for one cycle. Open to verify operation.,Thomas L. FloydD
3、igital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,4,Figure 84 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Sad
4、dle River, New Jersey 07458All rights reserved.,5,Figure 85 Four-bit asynchronous binary counter and its timing diagram. Open and verify the operation.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,6,Figure 8
5、6 An asynchronously clocked decade counter with asynchronous recycling.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,7,Figure 87 Asynchronously clocked modulus-12 counter with asynchronous recycling.,Thomas
6、L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,8,Figure 88 The 74LS93 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.),Thomas L.
7、 FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,9,Figure 89 Two configurations of the 74LS93 asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.),Thomas L. FloydDigital Fundamental
8、s, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,10,Figure 810 74LS93 connected as a modulus-12 counter.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,11
9、,Figure 811 A 2-bit synchronous binary counter.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,12,Figure 812 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flop
10、s are assumed to be equal).,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,13,Figure 813 Timing diagram for the counter of Figure 811.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Educatio
11、n, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,14,Figure 814 A 3-bit synchronous binary counter. Open to verify the operation.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,15,Figure 815 Timi
12、ng diagram for the counter of Figure 814.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,16,Figure 816 A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indi
13、cated by the shaded areas.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,17,Figure 817 A synchronous BCD decade counter. Open to verify operation.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pea
14、rson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,18,Figure 818 Timing diagram for the BCD decade counter (Q0 is the LSB).,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,19,Figure 81
15、9 The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.),Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,20,Figure 820 Timing example for a 74HC
16、163.,Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,21,Figure 821 The 74F162 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.),Thomas L. FloydDigital Fundamentals, 9e,Copyright 2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458All rights reserved.,22,Figure 822 Timing example for a 74F162.,Thomas L. FloydDigital Fun
