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1、第 9 讲 VHDL语言组合逻辑电路设计,电子设计自动化技术,一、逻辑门电路设计,例1：用数据流描述方式设计一个4输入“与或非”逻辑门,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY yhf4 IS PORT(A,B,C,D:IN STD_LOGIC; Y:OUT STD_LOGIC); END yhf4; ARCHITECTURE data_flow OF yhf4 IS BEGIN Y=NOT(A AND B) OR (C AND D); END data_flow;,请画出电路图,例2：设计一双向8位总线驱动器,LIBRARY IEEE
2、; USE IEEE.STD_LOGIC_1164.ALL; ENTITY qd8 IS PORT(A,B:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); EN,DIR:IN STD_LOGIC); END qd8; ARCHITECTURE behavior OF qd8 IS SIGNAL AOUT,BOUT:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN AB:PROCESS(A,EN,DIR) IF (EN=0) AND (DIR=1) THEN BOUT=A; ELSE BOUT=“ZZZZZZZZ”; END IF; B=BOUT;
3、END PROCESS AB;,为什么定义信号？,BA:PROCESS(B,EN,DIR) IF (EN=0) AND (DIR=0) THEN AOUT=B; ELSE AOUT=“ZZZZZZZZ”; END IF; END PROCESS BA; A=AOUT END behavior;,例2：设计一双向8位总线驱动器,二 编码器设计,例1：设计83优先权编码器,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY bmq83 IS PORT( D:IN STD_LOGIC_VECOR(7 DOWNTO 0); Y:OUT STD_LOGIC
4、_VECTOR(2 DOWNTO 0); END bmq83; ARCHITECTURE behavior OF bmq83 IS BEGIN PROCESS(D) BEGIN IF D(7)=0 THEN Y=“000”; ELSIF D(6)=0 THEN Y=“001”; ELSIF D(5)=0 THEN Y=“010”; ELSIF D(4)=0 THEN Y=“011”; ELSIF D(3)=0 THEN Y=“100”; ELSIF D(2)=0 THEN Y=“101”; ELSIF D(1)=0 THEN Y=“110”; ELSIF D(0)=0 THEN Y=“111”
5、; ELS Y=“XXX”; END PROCESS; END behavior;,该描述具有优先级,三 译码器设计,例1：设计38线译码器,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ymq83 IS PORT(A,B,C:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END ymq83;,请注意 数据类型的声明,ARCHITECTURE behavior OF ymq83 IS SIGNAL INDATA:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN IN
6、DATA Y Y Y Y Y Y Y Y Y=“XXXXXXXX”; END CASE; END PROCESS; END behavior;,该描述 不具有优先级,例：设计3 | 8线译码器,译码器设计,四、运算器设计,例1：设计4位二进制加法器,数据类型必须一致才能赋值,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY jfq4 IS PORT( a,b:IN STD_LOGIC_VECOR(3 DOWNTO 0);
7、 sum:OUT STD_LOGIC_VECTOR(4 DOWNTO 0); END jfq4; ARCHITECTURE behavior OF jfq4 IS BEGIN PROCESS(a,b) BEGIN sum=(0,例2：设计8位整数加法器,将数据类型转换为一致,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY jfq8 IS PORT( op1,op2: IN UNSIGNED(3 DOWNTO 0); result: OUT INTEGER); END jfq8; AR
8、CHITECTURE behavior OF jfq8 IS BEGIN result=CONV_INTEGER(OP1+OP2); END behavior;,四、运算器设计,五、奇偶校验电路设计,例1：设计9位奇偶校验电路，输入数据中“1”的个数为奇数时输出为“0”，否则输出为“1”。,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY jou9 IS PORT( a:IN STD_LOGIC_VECTOR(8 DOWNTO 0); y:OUT STD_LOGIC); END jou9;,ARCHITECTURE behavior OF ym
9、q83 IS BEGIN PROCESS(a) VARIABLE temp:STD_LOGIC; BEGIN temp:=1; FOR i IN 0 TO 8 LOOP temp:=temp XOR a(i); END LOOP; END PROCESS; y=temp; END behavior;,能否定义为信号？,例1：设计9位奇偶校验电路，输入数据中“1”的个数为奇数时输出为“0”，否则输出为“1”。,奇偶校验电路设计,六、已知真值表逻辑设计方法,例1：设计4选1数据选择器。,方法一：采用CASE语句 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
10、ENTITY xzq4_1 IS PORT( a,b:IN STD_LOGIC; i0,i1,i2,i3:IN STD_LOGIC; f:OUT STD_LOGIC); END xzq4_1;,ARCHITECTURE behavior OF ymq83 IS SIGNAL sel:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN selFFFFNULL; END CASE; END behavior;,为什么有OTHERS？,已知真值表逻辑设计方法,方法二：采用条件信号代入语句 ARCHITECTURE behavior OF ymq83 IS SIGNAL sel:S
11、TD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN sel=B,并行 or 顺序 描述？,已知真值表逻辑设计方法,方法三：采用IF语句 ARCHITECTURE behavior OF ymq83 IS SIGNAL sel:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN sel=B,有无优先级？,已知真值表逻辑设计方法,方法四：采用选择信号代入语句 ARCHITECTURE behavior OF ymq83 IS SIGNAL sel:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN sel=B,并行 or 顺序 描述？,已知
12、真值表逻辑设计方法,七、已知逻辑表达式设计方法,例1：设计1位全加器。,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY qjq1 IS PORT(A,B,C,CIN: IN STD_LOGIC; SUM,COUT: OUT STD_LOGIC); END qjq1; ARCHITECTURE data_flow OF qjq1 IS BEGIN PROCESS(A,B,CIN) BEGIN COUT=(A AND B)OR(A AND CIN)OR(B AND CIN); END PROCESS; SUM=A XOR B XOR CIN; E
13、ND data_flow;,注意 优先级,八、已知逻辑电路设计方法,例1：已知24线译码器电路。,请用数据流的方式设计,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ymq24 IS PORT(A0,A1:IN STD_LOGIC; Y0,Y1,Y2,Y3:OUT STD_LOGIC); END ymq24; ARCHITECTURE data_flow OF ymq24 IS BEGIN PROCESS(A0,A1) BEGIN Y0= Y1= Y2= Y3= END PROCESS; END data_flow;,Y0=NOT (NOT
14、 A1) AND (NOT A0); Y1=NOT (NOT A1) AND A0); Y2=NOT ( A1 AND (NOT A0); Y3=NOT (A1 AND A0);,已知逻辑电路设计方法,添加中间信号,已知逻辑电路设计方法,ARCHITECTURE dataflow OF ymq24 IS COMPONENT GINV PORT(A:IN STD_LOGIC; C:OUT STD_LOGIC); END COMPONENT; COMPONENT GNAND2 PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END COMPONENT; SIGNA
15、L L1,L2,L3,L4:STD_LOGIC; BEGIN U1:GINV PORT MAP(A0,L1); U2:GINV PORT MAP(A1,L2); U3:GINVPORT MAP(L1,L3); U4:GINVPORT MAP(L2,L4); U5:GNAND2 PORT MAP(L1,L2,Y0); U6:GNAND2 PORT MAP(L2,L3,Y1); U7:GNAND2 PORT MAP(L1,L4,Y2); U8:GNAND2 PORT MAP(L3,L4,Y3); END dataflow;,元件定义 元件在何处？,已知逻辑电路设计方法,LIBRARY IEEE;
16、USE IEEE.STD_LOGIC_1164.ALL; ENTITY GINV IS PORT(A:IN STD_LOGIC; C:OUT STD_LOGIC); END GINV; ARCHITECTURE dataflow OF GINV IS BEGIN C=NOT A; END dataflow;,元件设计应放在同一目录下,已知逻辑电路设计方法,元件设计应放在同一目录下,已知逻辑电路设计方法,LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY GNAND2 IS PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END GNAND2; ARCHITECTURE dataflow OF GNAND2 IS BEGIN C=NOT (A AND B); END dataflow;,
