《电子与通信专业英语 第八讲课件》由会员分享，可在线阅读，更多相关《电子与通信专业英语 第八讲课件（29页珍藏版）》请在金锄头文库上搜索。
1、电子与通信专业英语 Unit 8: A Hybrid ASIC and FPGA Architecture,电子工程学院 温志刚 ,Unit 8,A Hybrid ASIC and FPGA Architecture ASIC 和 FPGA 混合结构,词汇: ASIC- Application Specific Integrated Circuits(专用集成电路). FPGA- Field-programmable Gate Array(现场可编程门阵列) CPLD- Complex Programmable Logic Device(复杂可编程逻辑器件) VHDL- Very-High-S
2、peed Integrated Circuit Hardware Description Language(超高速集成电路硬件描述语言)美国国防部 Verilog HDL- 美国Candence design systems,Implementation using an ASIC approach typically yields a faster, smaller, and lower power design than implementation in FPGA technology. The growing requirements in the marketplace for de
3、sign flexibility however, are driving the need for hybrid ASIC/FPGA devices. The potential to change hardware configuration in real time, to support multiple design options with a single mask set, and to prolong a products usable life, all compel designers to look for a blending of high density ASIC
4、 circuits along with the inherent FPGA circuit flexibility 1.,8.1 Applications Emerge for Hybrid Devices,词汇: compel-to force somebody to do something. blendingwith -combining,The ability to create a “base design” and then reuse the base with minimal changes for subsequent devices helps reduce design
5、 time and encourages standardization. Since many consumer and office products are offered with a range of low to high-end options, this base design concept can be effectively used with features added to each successive model. Printers, fax machines, PCs and digital imaging equipment are examples whe
6、re this concept can be useful.,8.1 Applications Emerge for Hybrid Devices,DSP applications are also well suited to FPGA because of the FPGAs fast multiply and accumulate (MAC) processing capability. When building a DSP system, the design can take advantage of parallel structures and arithmetic algor
7、ithms to minimize resources and exceed performance of single or multiple purpose DSP devices. DSP designers using both ASIC and FPGA within the same design can optimize a system for performance beyond the capabilities of either separate circuit technology.,8.1 Applications Emerge for Hybrid Devices,
8、词汇: compel-to force somebody to do something. blendingwith -combining,Other applications that lend themselves to the hybrid ASIC/FPGA approach are designs that support multiple standards such as USB, FireWire and CameraLink, in a single device. Similarly, designs that are finalized, with the excepti
9、on of any undefined features or emerging standard, are excellent candidates for this technology. Without the benefit of programmable logic, the designer must decide between taping-out the chip knowing that the PCI logic has a high probability for change, or waiting until the design requirements are
10、firm potentially impacting the end products schedule 2. With both programmable logic and ASIC working together on a single device, some situations like these can be accommodated. Other similar issues like differing geographic or I/O standards could also be incorporated within the FPGA cores, without
11、 requiring mask and fabrication updates for each change.,8.1 Applications Emerge for Hybrid Devices,While technical applications are emerging for the hybrid architecture, it is unlikely that design teams would utilize this new capability unless it is also economically viable. We will now explore the
12、 economics behind this new architecture. To realize the performance and density advantages of an ASIC, design teams must accept higher NREs and longer TATs than FPGAs. Unlike off-the-shelf FPGAs, each ASIC design requires a custom set of masks for silicon fabrication.,8.2 Economics Play a Role in Us
13、ing Hybrid Devices,词汇: NRE- (Non Recurring Engineering) 非重复性工程成本.即新的集成电路产品的研制开发费 TATs - (Turn Around Time) 周转时间 off-the-shelf- already made and available in shops rather than being designed especially for a customer,The custom mask set allows circuitry and interconnections to be tailored to the requ
14、irements of each unique application yielding high performance and density. However, the cost of the mask sets is rapidly increasing (nearly doubling with each successive technology node). As a result, mask costs are becoming a significant portion of the per-die cost in many cases.,8.2 Economics Play
15、 a Role in Using Hybrid Devices,For example, consider the case where a mask set costs $1,000,000. For applications where only 1,000 chips are required, each chip will cost well over $1000, since the mask cost (plus many other expenses) must be amortized over the volume of chips sold. As the volume r
16、equirements for this same ASIC rise, the effective cost of each die decreases.,Conversely, FPGAs are standard products, where the mask charges for a small number of design passes are amortized over a large number of customers and chips, so the mask cost per chip sold is minimal. As a result, for each technology node there is a volume threshold, below which its more cost-effective to buy an FPGA chip vs. a smaller ASIC chip. TAT is another primary economic dri
