《第3章智力抢答器的设计与分析上课讲义》由会员分享，可在线阅读，更多相关《第3章智力抢答器的设计与分析上课讲义（34页珍藏版）》请在金锄头文库上搜索。
1、第3章 智力抢答器的设计与分析,3.1 系统设计要求 3.2 系统设计方案 3.3 主要VHDL源程序 3.4 系统仿真/硬件验证 3.5 设计技巧分析 3.6 系统扩展思路,3.1 系统设计要求,在许多比赛活动中，为了准确、公正、直观地判断出第一抢答者，通常设置一台抢答器，通过数显、灯光及音响等多种手段指示出第一抢答者。同时，还可以设置计分、犯规及奖惩计录等多种功能。本设计的具体要求是：,(1) 设计制作一个可容纳四组参赛者的数字智力抢答器，每组设置一个抢答按钮供抢答者使用。 (2) 电路具有第一抢答信号的鉴别和锁存功能。 (3) 设置计分电路。 (4) 设置犯规电路。,3.2 系统设计方案
2、,根据系统设计要求可知，系统的输入信号有：各组的抢答按钮A、B、C、D，系统清零信号CLR，系统时钟信号CLK，计分复位端RST，加分按钮端ADD，计时预置控制端LDN，计时使能端EN，计时预置数据调整按钮TA、TB；系统的输出信号有：四个组抢答成功与否的指示灯控制信号输出口LEDA、LEDB、LEDC、LEDD，四个组抢答时的计时数码显示控制信号若干，抢答成功组别显示的控制信号若干，各组计分动态显示的控制信号若干。,图3.1 智力抢答器的组成框图,3.3 主要VHDL源程序,3.3.1 抢答鉴别电路QDJB的VHDL源程序 -QDJB.VHD LIBRARY IEEE; USE IEEE.S
3、TD_LOGIC_1164.ALL; ENTITY QDJB IS PORT(CLR: IN STD_LOGIC; A, B, C, D: IN STD_LOGIC; A1,B1,C1,D1: OUT STD_LOGIC; STATES: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);,END ENTITY QDJB; ARCHITECTURE ART OF QDJB IS CONSTANT W1: STD_LOGIC_VECTOR: =0001; CONSTANT W2: STD_LOGIC_VECTOR: =0010; CONSTANT W3: STD_LOGIC_VE
4、CTOR: =0100; CONSTANT W4: STD_LOGIC_VECTOR: =1000; BEGIN PROCESS(CLR,A,B,C,D) IS BEGIN,IF CLR=1 THEN STATES=0000; ELSIF (A=1AND B=0AND C=0AND D=0) THEN A1=1; B1=0; C1=0; D1=0; STATES=W1; ELSIF (A=0AND B=1AND C=0AND D=0) THEN A1=0; B1=1; C1=0; D1=0; STATES=W2; ELSIF (A=0AND B=0AND C=1AND D=0) THEN A1
5、=1; B1=0; C1=1; D1=0; STATES=W3; ELSIF (A=0AND B=0AND C=0AND D=1) THEN A1=0; B1=0; C1=0; D1=1; STATES=W4; END IF; END PROCESS; END ARCHITECTURE ART;,3.3.2 计分器电路JFQ的VHDL源程序 -JFQ.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JFQ IS PORT(RST: IN STD_LOGIC; ADD:
6、IN STD_LOGIC; CHOS: IN STD_LOGIC_VECTOR(3 DOWNTO 0); AA2,AA1,AA0,BB2,BB1,BB0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);,CC2,CC1,CC0,DD2,DD1,DD0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END ENTITY JFQ ; ARCHITECTURE ART OF JFQ IS BEGIN PROCESS(RST,ADD,CHOS) IS VARIABLE POINTS_A2,POINTS_A1: STD_LOGIC_VECTOR(3 DOWNT
7、O 0); VARIABLE POINTS_B2,POINTS_B1: STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE POINTS_C2,POINTS_C1: STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE POINTS_D2,POINTS_D1: STD_LOGIC_VECTOR(3 DOWNTO 0);,BEGIN IF (ADDEVENT AND ADD=1) THEN IF RST=1 THEN POINTS_A2: =0001; POINTS_A1: =0000; POINTS_B2: =0001; POINTS_B1:
8、=0000; POINTS_C2: =0001; POINTS_C1: =0000; POINTS_D2: =0001; POINTS_D1: =0000; ELSIF CHOS=0001 THEN,IF POINTS_A1=1001 THEN POINTS_A1: =0000; IF POINTS_A2=1001 THEN POINTS_A2: =0000; ELSE POINTS_A2: =POINTS_A2+1; END IF; ELSE POINTS_A1: =POINTS_A1+1; END IF; ELSIF CHOS=0010 THEN,IF POINTS_B1=1001 THE
9、N POINTS_B1: =0000; IF POINTS_B2=1001 THEN POINTS_B2: =0000; ELSE POINTS_B2: =POINTS_B2+1; END IF; ELSE POINTS_B1: =POINTS_B1+1; END IF;,ELSIF CHOS=0100 THEN IF POINTS_C1=1001 THEN POINTS_C1: =0000; IF POINTS_C2=1001 THEN POINTS_C2: =0000; ELSE POINTS_C2: =POINTS_C2+1; END IF; ELSE POINTS_C1: =POINT
10、S_C1+1; END IF;,ELSIF CHOS=1000 THEN IF POINTS_D1=1001 THEN POINTS_D1: =0000; IF POINTS_D2=1001 THEN POINTS_D2: =0000; ELSE POINTS_D2: =POINTS_D2+1; END IF; ELSE POINTS_D1: =POINTS_D1+1;,END IF; END IF; END IF; AA2=POINTS_A2; AA1=POINTS_A1; AA0=0000; BB2=POINTS_B2; BB1=POINTS_B1; BB0=0000; CC2=POINT
11、S_C2; CC1=POINTS_C1; CC0=0000; DD2=POINTS_D2; DD1=POINTS_D1; DD0=0000; END PROCESS; END ARCHITECTURE ART;,3.3.3 计时器电路JSQ的VHDL源程序 -JSQ.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JSQ IS PORT(CLR,LDN,EN,CLK: IN STD_LOGIC; TA,TB: IN STD_LOGIC; QA: OUT STD_LOGI
12、C_VECTOR(3 DOWNTO 0); QB: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);,END ENTITY JSQ; ARCHITECTURE ART OF JSQ IS SIGNAL DA: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL DB: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(TA,TB,CLR) IS BEGIN IF CLR=1 THEN DA=0000; DB=0000; ELSE,IF TA=1 THEN DA=DA+1 ; END IF; IF TB=1 THEN
13、DB=DB+1; END IF; END IF; END PROCESS; PROCESS(CLK) IS VARIABLE TMPA: STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE TMPB: STD_LOGIC_VECTOR(3 DOWNTO 0);,BEGIN IF CLR=1 THEN TMPA: =0000; TMPB: =0110; ELSIF CLKEVENT AND CLK=1 THEN IF LDN=1 THEN TMPA: =DA; TMPB: =DB; ELSIF EN=1 THEN IF TMPA=0000 THEN TMPA: =100
14、1; IF TMPB=0000 THEN TMPB: =0110; ELSE TMPB: =TMPB-1;,END IF; ELSE TMPA: =TMPA-1; END IF; END IF; END IF; QA=TMPA; QB=TMPB; END PROCESS; END ARCHITECTURE ART;,3.3.4 译码器电路YMQ的VHDL源程序 -YMQ.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY YMQ IS PORT(AIN4: IN STD_L
15、OGIC_VECTOR(3 DOWNTO 0); DOUT7: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); END YMQ; ARCHITECTURE ART OF YMQ IS,BEGIN PROCESS(AIN4) BEGIN CASE AIN4 IS WHEN 0000=DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7DOUT7=1111101; -6,WHEN 0111=DOUT7DOUT7DOUT7DOUT7=0000000; END CASE; END PROCESS; END ARCHITECTURE ART;,3.4 系统仿真/硬件验证,3.4.1 系统的有关仿真 系统仿真后的结果分别如图3.2、图3.3、图3.4、图3.5所示。,图3.2 抢答鉴别电路QDJB仿真图,图3.3 计分器电路JFQ仿真图,图3.4 计时器电路JSQ仿真图,图3.5 译码器电路YMQ仿真图,3.4.2 系统的硬件验证 请读者根据自己所拥有的实验设备自行完成。,3.5 设计技巧分析,(1) 在抢答鉴别电路的设计中，A、B、C、D四组抢答，理论上应该有16种可能情况，但实际上由于芯片的反应速度快到一定程度时，两
