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1、7-937CAUTION:Thesedevicesaresensitivetoelectrostaticdischarge;followproperICHandlingProcedures.1-888-INTERSILor321-724-7143|CopyrightIntersilCorporation1999CD4051BMS,CD4052BMSCD4053BMSCMOSAnalogMultiplexers/Demultiplexers*DescriptionCD4051BMS,CD4052BMSandCD4053BMSanalogmulti-plexers/demultiplexersar
2、edigitallycontrolledanalogswitcheshavinglowONimpedanceandverylowOFFleak-agecurrent.Controlofanalogsignalsupto20Vpeak-to-peakcanbeachievedbydigitalsignalamplitudesof4.5Vto20V(ifVDD-VSS=3V,aVDD-VEEofupto13Vcanbecon-trolled;forVDD-VEEleveldifferencesabove13V,aVDD-VSSofatleast4.5Visrequired).Forexample,
3、ifVDD=+4.5V,VSS=0,andVEE=-13.5V,analogsignalsfrom-13.5Vto+4.5Vcanbecontrolledbydigitalinputsof0to5V.ThesemultiplexercircuitsdissipateextremelylowquiescentpoweroverthefullVDD-VSSandVDD-VEEsupplyvoltageranges,independentofthelogicstateofthecontrolsignals.Whenalogic“1”ispresentattheinhibitinputterminal
4、allchannelsareoff.TheCD4051BMSisasingle8channelmultiplexerhavingthreebinarycontrolinputs,A,B,andC,andaninhibitinput.Thethreebinarysignalsselect1of8channelstobeturnedon,andconnectoneofthe8inputstotheoutput.TheCD4052BMSisadifferential4channelmultiplexerhav-ingtwobinarycontrolinputs,AandB,andaninhibiti
5、nput.Thetwobinaryinputsignalsselect1of4pairsofchannelstobeturnedonandconnecttheanaloginputstotheout-puts.TheCD4053BMSisatriple2channelmultiplexerhavingthreeseparatedigitalcontrolinputs,A,B,andC,andaninhibitinput.Eachcontrolinputselectsoneofapairofchan-nelswhichareconnectedinasinglepoledouble-throwco
6、n-figuration.TheCD4051BMS,CD4052BMSandCD4053BMSaresuppliedinthese16leadoutlinepackages:BrazeSealDIP*H4XH4TFritSealDIPH1ECeramicFlatpackH6W*CD4051BOnlyCD4052B,CD4053OnlyFeaturesLogicLevelConversionHigh-VoltageTypes(20VRating)CD4051BMSSignal8-ChannelCD4052BMSDifferential4-ChannelCD4053BMSTriple2-Chann
7、elWideRangeofDigitalandAnalogSignalLevels:-Digital3Vto20V-Analogto20Vp-pLowONResistance:125(typ)Over15Vp-pSignalInputRangeforVDD-VEE=15VHighOFFResistance:ChannelLeakageof100pA(typ)atVDD-VEE=18VLogicLevelConversion:-DigitalAddressingSignalsof3Vto20V(VDD-VSS=3Vto20V)-SwitchAnalogSignalsto20Vp-p(VDD-VE
8、E=20V);SeeIntroductoryTextMatchedSwitchCharacteristics:RON=5(typ)forVDD-VEE=15VVeryLowQuiescentPowerDissipationUnderAllDigi-talControlInputandSupplyConditions:0.2W(typ)atVDD-VSS=VDD-VEE=10VBinaryAddressDecodingonChip5V,10Vand15VParametricRatings100%TestedforQuiescentCurrentat20VMaximumInputCurrentof
9、1Aat18VOverFullPack-ageTemperatureRange;100nAat18Vand+25oCBreak-Before-MakingSwitchingEliminatesChannelOverlapApplicationsAnalogandDigitalMultiplexingandDemultiplexingA/DandD/AConversionSignalGating*Whenthesedevicesareusedasdemultiplexersthe“CHANNELIN/OUT”terminalsaretheoutputsandthe“COMMONOUT/IN”te
10、r-minalsaretheinputs.FileNumber3316December19927-938CD4051BMS,CD4052BMS,CD4053BMSPinoutsCD4051BMTOPVIEWCD4052BMSTOPVIEWCD4053BMSTOPVIEWFunctionalDiagramsCD4051BMS14151691312111012345768CHANNELS6COMOUT/IN75INHVSSVEEVDD103ABC2IN/OUT4CHANNELSIN/OUTCHANNELSIN/OUT14151691312111012345768YCHANNELS2COMMON“Y
11、”OUT/IN31INHVSSVEEVDD1COMMON“X”OUT/IN03AB2IN/OUT0YCHANNELSIN/OUTXCHANNELSIN/OUTXCHANNELSIN/OUT14151691312111012345768bxcyOUT/INCXorCYIN/OUTCXINHVSSVEEVDDOUT/INaxorayayaxABCOUT/INbxorbyIN/OUTbyIN/OUT7LOGICLEVELCONVERSIONBINARYTO1OF8DECODERWITHINHIBITTGTGTGTGTGTGTGTG3689101116VEEVSS*ABCINHVDDCOMMONOUT
12、/INCHANNELIN/OUT12451213141576543210VDDVSS*ALLINPUTSPROTECTEDBYSTANDARDCMOSPROTECTIONNETWORK7-939CD4051BMS,CD4052BMS,CD4053BMSCD4052BMSCD4053BMSFunctionalDiagrams(Continued)7LOGICLEVELCONVERSIONBINARYTO1OF4DECODERWITHINHIBITTGTGTGTGTGTGTGTG36891016VEEVSS*ABINHVDDCOMMONYOUT/INXCHANNELSIN/OUT111214153
13、210YCHANNELSIN/OUT14250123COMMONXOUT/IN137LOGICLEVELCONVERSIONTGTGTGTGTGTG98101116VEEVSS*ABCVDDIN/OUT112132bybxayaxOUT/INbxorby35cycx41514OUT/INaxorayOUT/INcxorcy6*INHBINARYTO1OF2DECODERSWITHINHIBITVDDVSS*ALLINPUTSPROTECTEDBYSTANDARDCMOSPROTECTIONNETWORK7-940SpecificationsCD4051BMS,CD4052BMS,CD4053B
14、MSAbsoluteMaximumRatingsReliabilityInformationDCSupplyVoltageRange,(VDD).-0.5Vto+20V(VoltageReferencedtoVSSTerminals)InputVoltageRange,AllInputs.-0.5VtoVDD+0.5VDCInputCurrent,AnyOneInput.10mAOperatingTemperatureRange.-55oCto+125oCPackageTypesD,F,K,HStorageTemperatureRange(TSTG).-65oCto+150oCLeadTemp
15、erature(DuringSoldering).+265oCAtDistance1/161/32Inch(1.59mm0.79mm)fromcasefor10sMaximumThermalResistance.jajcCeramicDIPandFRITPackage.80oC/W20oC/WFlatpackPackage.70oC/W20oC/WMaximumPackagePowerDissipation(PD)at+125oCForTA=-55oCto+100oC(PackageTypeD,F,K).500mWForTA=+100oCto+125oC(PackageTypeD,F,K).D
16、erateLinearityat12mW/oCto200mWDeviceDissipationperOutputTransistor.100mWForTA=FullPackageTemperatureRange(AllPackageTypes)JunctionTemperature.+175oCTABLE1.DCELECTRICALPERFORMANCECHARACTERISTICSPARAMETERSYMBOLCONDITIONS(NOTE1)GROUPASUBGROUPSTEMPERATURELIMITSUNITSMINMAXSupplyCurrentIDDVDD=20V,VIN=VDDorGND1+25oC-10A2+1
