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1、MIPIDSIEssential 2 TableofContents MIPIDSIOverviewPHYLayerD PHYArchitectureGlobalOperationLaneManagementLayerDSIProtocolLayer MIPIDSIOverview SerialInterfaceLowPinCountReducedPowerConsumption2TypesofDataSignalingHighSpeedDataTransmission 500Mbps Lane differentialsignalingLowPowerDataTransmission 10M
2、bps singleendedsignaling lane0onlyLane Scalable upto4datalanesPacketBasedDataTransmissionDSIProtocolhasECC CRCcapability robustdatatransmissionProtocolSupportMultipledisplays upto4 SupportAllLegacyParallelInterfaceFunctionalityMIPIDSICommandMode MIPIDBIInterface I 80Interface MIPIDSIVideoMode MIPIDP
3、IInterface RGBInterface 4 MIPIDSIInterfacePhysicalArchitecture 1ClockLane unidirectional 1to4DataLanes Lane0isbidirectionalforLPdataoutputtransmissionofthedriverIC 5 MIPIDSIFunctionalLayers TransmitterSide N 8 bits ReceiverSide PHYLayer Data3 Control PHYLayer Control Data2 Data1 Data0 N 8 bits Data1
4、 Data3 Data3 Data0 HighSpeedUnidirectionalClockLane0 HighSpeedbidirectionalDataLane1 HighSpeedUnidirectionalDataLane2 HighSpeedUnidirectionalDataLane3 HighSpeedUnidirectionalData PhysicalTransmission ReceptionSerializer DeserializerByteClockGeneration Recovery DDR perMIPID PHYSpec 6 VideoModeDisplay
5、 DisplayDriver HostProcessor DisplayPanel LCDDisplay BusInterface BusInterface ColorFrameBuffer DisplayRefresh TimingControl UpdateFrameBuffer 7 CommandModeDisplay HostProcessor DisplayPanel LCDDisplay BusInterface ColorFrameBuffer ImageUpdateData Commands ImageUpdateData BusInterface DisplayControl
6、ler PHYLayer D PHYArchitecture 9 PHYLaneConfiguration MinimumConfigurationAtleast1ClockLane 1DataLaneReverse directiontrafficuseslane0onlyLane1 2 3 ifpresent areunidirectionalLanenumberfixedatdesign manufacture Modulelevel Nodynamiclaneconfigurationbyhostprocessor 10 D PHYLaneModule 1 2 Transmission
7、dataUnitOnebyteLaneModulemaycontainHS TX HS RX orbothIfLPmodeisusedatcommandmodeconfiguration bothhostandperipheralmustincludeLPRxandLPTxAlsoCDneededifbi directionalinuseTheLP CDshallcheckforcontentionatleastoncebeforedrivinganewstateonthelineMasterandaSlaveconcept 11 D PHYLaneModule 2 2 Lowpowertra
8、nsmitter Highspeedreceiver Lowpowerreceiver Contention collision detection Highspeedtransmitter 12 LeastPHYLaneConfiguration DetailedView Datalane0 CLKlane Bi directionalbutnotHSreverse LPforbi directional uni directional LPforminimumtransitioncontrol 13 D PHYSignalLevel 2TypesofSignalLevelHSDTLPDT
9、LPVOH typ1 2V 1 1V 1 3V HSdiff typ200mv 140mv 270mv HScomm typ200mv 150mv 250mv LPVOH typ0V 50mV 50mV LPVIL 550mV LPVIH typ1 2v0 88V 1 35V 14 HSMode TransmitterReceiverStructure HSDataTransmissionWhileHSDTisactive TerminationRisenabled 15 HSMode SignalingDetailedView 300mv 100mv 200mv 100mv 200mv Vd
10、iff VOD Vdiff200mV Vcm200mVTypCondition 16 HSMode ClockTransmission HSClockDDRClockStructure 1ClkPeriod 2 UIClockBurstalwayscontainsanevennumberoftransitionClockcanalsorunwhileD0isinLPmode especiallyVideomode Ex 500MbpsFreq 250Mhz 1ClkPeriod 4ns IU 2ns 17 HSMode ClocktoData DatatoClockTimingDefiniti
11、on90DegreePhaseShiftCLKtoDataTheFirstbitofDSIPacketmustbesentatarisingedgeofHSClk DataLane ClockLane 18 HSDTSignalinPractice VCM 200mVnom Vo typically 300mV Vo typically 100mV Vdiff positive 19 LPSignalingDetailedView Typically1 2VTLPX min 50ns 20 LPDTSignalinPractice 2TLPX typically1 2V DP DN PHYLa
12、yer GlobalOperation 22 DataUnitOfD PHY MinimumDataUnitis1ByteTransmitter Bytestream BitstreamReceiver Bitstream BytestreamHSLanecanbedifferential1or0LPLaneonD0canhavefourstate LP LP00 Bridge Space LP01 HS Rqst Mark 0 LP10 LP Rqst Mart 1 LP11 Stop 23 D PHYOperationFlowDiagram LP 11 Stop StateThestart
13、stateofeveryoperation MajorThreeTypeModesEscapeModeHSTBusTurnAroundPHYStateisdecidedbyLPstateHSDT LP11 LP01 LP00 HSDT LP 11LPDT LP11 LP10 LP00 EscapeMode LP11InCaseofClockLaneHSTisSupportedforClockSupply 24 EscapeModeOperation EscapeModeEntry EscapeModeLeaveEscapeModeCommands 25 EscapeModeOperation
14、LPDT LowPowerDataTransmission 26 EscapeModeOperation ResetTrigger UltraLowPowerState 27 EscapeModeinPractice LPDT EMELP11 LP10 LP00 LP01 LP00 EscapeModeCommandLPDT11100001 0 x87 Data1 10011100 0 x39 PacketHeader DP DN 28 HSModeOperation HighSpeedDataTransmissionRequestLP11 LP01 LP00Clock DataLane Sa
15、meEntryHighSpeedClockLaneisstartedbeforeDataTransmission 29 HSModeOperation DataLaneEntry LowPowerModetoHighSpeedModeLP11 LP01 LP00 SOT HSDTSynchronizationCode 00011101DataTransmission 30 HSModeOperation DataLaneLeave LowPowerModetoHighSpeedModeHSDT EOT LP11 31 HSModeOperationinPractice LPDTtoHSDT L
16、P01 LP00 LP11 LPTransmitterDriving HSTransmitterDriving HSClock R termOn DP DN 32 HSModeOperationinPractice SOT SOT00011101 DATA0 Clk Data 33 BusTurnAround HandoverBusPossessionHosttoclient clienttohostWhenhostrequestdatafromclientandwhenhostreadstatusofclientClientmustsendBTAafterclient sdatatransmissionTE signalingSequence ex ReadRequesttoClient HostSend ReadRequest toClient HostsendsBTA ClientGetBus HostReleasesBus Clientsendsdata ClientsendsBTA HostGetBusLP11 LP10 LP00 LP10 LP00 34 BusTurnAr
