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1、1 The DSP Primer Presented by Bob Stewart University of Strathclyde Scotland UK r stewart eee strath ac uk Steve Alexander University of Strathclyde Scotland UK salexander eee strath ac uk Jeff Weintraub Xilinx Inc San Jose USA jeff weintraub Presented as part of Xilinx University Program XUP August
2、 2005 Version 0 97 2 3 Xilinx DSP Primer WorkBook Contents Page 1Introduction 5 1 1Software Required 5 1 2Example Files and Directories 6 1 3Shorthand for Mouse Clicks 6 2Top Level View of the Design Flow 6 2 1Virtex2 XC2V40 Target FPGA 7 2 2Running a SystemGenerator Simulation 7 3Simple Arithmetic
3、20 3 1What Hardware Cost is Saturate 22 3 2Complex Arithmetic 25 4Designing for Xilinx ISE Tools 27 4 1Building Delays Lines 40 4 2Arithmetic Components 41 5FIR filtering 43 5 1Wordlength growth 43 6FIR Digital Filter by Multiplier Block Synthesis 49 6 1Inside the Multiplier Block 50 7Adaptive Filte
4、ring 53 8Low Pass Cascaded Integrator Comb CIC Filters 56 8 1CIC filters 57 9Direct Digital Downconversion 61 9 1Downconversion using DSP 61 9 2CICs for Downconversion 64 10 Numerically Controlled Oscillators 66 10 1 Look up Table Technique 66 10 2 Sine Wave Generation Using IIR Filters 68 11 CORDIC
5、 Vector Magnitude Calculations 74 11 1 The Golden Reference Design 74 11 2 The Fixed Point CORDIC Design 75 11 3 Build A Fixed Point CORDIC System 81 11 4 Using CORDIC In A QR Array 82 12Fixed Point Sigma Delta 85 13Fixed Point Bandlimiting RRC Filtering 86 14 FPGA as an ASIC Digital Downconverter 8
6、9 4 51 Introduction 1Introduction In this DSP for FPGAs Primer workbook the aim is To allow all users experience of using the entire toolchain from DSP algorithm concept to FPGA implementation After completing this workbook you will be able to Understand fundamental DSP algorithms for FPGA implement
7、ation Be aware of the FPGA hardware for implementation of DSP algorithms Know how to use Simulink and SystemGenerator for the simulation of DSP algorithms architectures and systems Know how to correctly design a DSP system with knowledge of issues relating to wordlengths overflow saturation wraparou
8、nd and so on Be able to take a design from Simulink System Generator implementation to Xilinx ISE tools Know how to use Xilinx ISE tools to synthesize and place and route the design Know how to use the Xilinx FPGA editor to inspect the actual hardware implementation with respect to on chip hardware
9、Know how to perform hardware in the loop simulation Know how to run DSP algorithms on the XUP Virtex 2 Pro board 1 1Software Required The following software is required to complete the various examples in this workbook 1 MatLab Release 14 Simulink 6 2 Xilinx System Generator v7 1 3 Xilinx ISE Tools
10、v7 1 ServicePack 3 IP update 4 Xilinx Chipscope v7 1 If any of these are missing please contact the appropriate vendor for install files and a licence We will be using Xilinx ISE tools for synthesis and HDL simulation It is of course possible to use other synthesis tools Leonardo Synplicity to do th
11、ese stages 6 1 2Example Files and Directories The examples for this workbook should be copied to the location c Xilinx DSP Primer As a short cut notation we will use the Xilinx symbol to specify the directory c Xilinx DSP Primer You will note that all top level Simulink models with the mdl suffix ar
12、e usually located in a directory with the same name For example the Simulink model shortfilter mdl would be found in directory shortfilter shortfilter mdl or c Xilinx DSP Primer shortfilter shortfilter mdl The reason for placing the examples in their own named directory is to ensure that if you deci
13、de to set up a Xilinx ISE project file then there is no interaction or mixing of different ISE project files which could happen if the ISE tools were used on two or more different mdl files in the same directory 1 3Shorthand for Mouse Clicks Shorthand symbols for mouse clicks will be used in this wo
14、rkbook according to the table below 2Top Level View of the Design Flow In this section we take some very simple designs through the entire design flow from simulation to bitstream form ready for implementation on an FPGA 21 H 1 Left mouse button click once Right mouse button click onceLeft mouse but
15、ton click twice Left mouse button hold down Right mouse button hold down H Figure 1 1 Mouse and keyboard click notation used in this document Right mouse button click once 2 72 Top Level View of the Design Flow 2 1Virtex2 XC2V40 Target FPGA For these first exercises we will use a small device the Xi
16、linx Virtex2 XC2V40 device and go from simple DSP implementation to actual floorplanning on the device We have chosen this device in order to be able to easily inspect the DSP implementation on the FPGA Later in the workbook we will be working with the larger XCVP30 device which is available on the actual board use in this course Some of the key features of this device are given in the table below next to a comparison of some of the other parts from the Xilinx family 2 2Running a SystemGenerator
