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1、Mixed Analog and Digital Integrated Circuit Design 8 O or qli f E 2009 2010 c Li Qiang UESTC SCIE Mixed Analog and Digital IC DesignLecture 10 Fall 20091 66 Administratives Administrative Issues Lecture time change Dec 17 5 6th Thu pm Cancelled Postponed Dec 22 5 6th Tue pm Cancel possibly TBD Dec 2
2、9 5 6th Tue pm Cancel possibly TBD Project topics 10 b 200 MS s ADC 14 b 20 MS s ADC 12 b 200 MS s DAC Examination 1 5 students group Project presentation week 20 Jan 12 VVV CC EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 44 Switch Charge Injection VVV CC EECS 247 Lecture 17 Nyquist
3、Rate ADCs Sampling 2008 H K Page 44 Switch Charge Injection Clock Feedthrough Slow Clock Example VG t VH Vi VL Vi Vth VO Vi toff V t Vi VO Cs 1pF M1 VG 10 0 18 t 2 ov oxthL ov s ov osthL s C0 1fF C9 fF V0 4VV0 C10 x0 1fF 1 C1pF Allowing1 2LSBADC resolution 9bit C VVV0 4mV C Li Qiang UESTC SCIE Mixed
4、 Analog and Digital IC DesignLecture 10 Fall 200959 66 Analog to Digital ConvertersCharge Injection Clock Feedthrough EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 45 Switch Charge Injection Clock Feedthrough Fast Clock VG t VH Vi VL Vi Vth VO Vi toff V t Vi VO Cs 1pF M1 VG Sudden gat
5、e voltage drop no gate voltage to establish current in channel channel charge has no choice but to escape out towards S D Qch mQch nQch n m 1 EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 46 For simplicity it is assumed channel charge divided equally between S D Source of error channe
6、l charge transfer clock feedthrough via CovtoCs VG t VH Vi VL Vi Vth VO Vi toff V t Switch Charge Injection Clock Feedthrough Fast Clock Clock Fall Time Device Speed ovch oHL ovss oxHithov HL ovss oios ox s oxHthov osHL ss C1Q VVV CC2C WC L VVVC1 VV CC2C VV 1V 1 WC L where 2C WC L VVC1 VVV C2C Li Qi
7、ang UESTC SCIE Mixed Analog and Digital IC DesignLecture 10 Fall 200960 66 Analog to Digital ConvertersCharge Injection Clock Feedthrough EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 45 Switch Charge Injection Clock Feedthrough Fast Clock VG t VH Vi VL Vi Vth VO Vi toff V t Vi VO Cs
8、1pF M1 VG Sudden gate voltage drop no gate voltage to establish current in channel channel charge has no choice but to escape out towards S D Qch mQch nQch n m 1 EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 46 For simplicity it is assumed channel charge divided equally between S D So
9、urce of error channel charge transfer clock feedthrough via CovtoCs VG t VH Vi VL Vi Vth VO Vi toff V t Switch Charge Injection Clock Feedthrough Fast Clock Clock Fall Time Device Speed ovch oHL ovss oxHithov HL ovss oios ox s oxHthov osHL ss C1Q VVV CC2C WC L VVVC1 VV CC2C VV 1V 1 WC L where 2C WC
10、L VVC1 VVV C2C Li Qiang UESTC SCIE Mixed Analog and Digital IC DesignLecture 10 Fall 200961 66 Analog to Digital ConvertersCharge Injection Clock Feedthrough EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 47 Switch Charge Injection Clock Feedthrough Fast Clock Example Vi VO Cs 1pF M1 V
11、G 10 0 18 ovoxthDDL 2 2 ox s oxHthov osHL ss fFfF C0 1 C9 V0 4V V1 8V V0 WLC10 x0 18 x9 fF 1 21 6 5bit C1pF WC L VVC1 VVV1 8mV14 6mV16 4mV C2C VG t VH Vi VL Vi Vth VO Vi toff V t EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 48 Vo V Vi Switch Charge Injection Clock Feedthrough Slow Cl
12、ock versus Fast Clock Slow Clock Vo V Vi Fast Clock Li Qiang UESTC SCIE Mixed Analog and Digital IC DesignLecture 10 Fall 200962 66 Analog to Digital ConvertersCharge Injection Clock Feedthrough EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 47 Switch Charge Injection Clock Feedthrough
13、 Fast Clock Example Vi VO Cs 1pF M1 VG 10 0 18 ovoxthDDL 2 2 ox s oxHthov osHL ss fFfF C0 1 C9 V0 4V V1 8V V0 WLC10 x0 18 x9 fF 1 21 6 5bit C1pF WC L VVC1 VVV1 8mV14 6mV16 4mV C2C VG t VH Vi VL Vi Vth VO Vi toff V t EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 48 Vo V Vi Switch Charg
14、e Injection Clock Feedthrough Slow Clock versus Fast Clock Slow Clock Vo V Vi Fast Clock Li Qiang UESTC SCIE Mixed Analog and Digital IC DesignLecture 10 Fall 200963 66 Analog to Digital ConvertersCharge Injection Clock Feedthrough EECS 247 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 49 Swit
15、ch Charge Injection Clock Feedthrough Example Summary Error function of Clock fall time Input voltage level Source impedance Sampling capacitance size Switch size Clock fall rise should be controlled not to be faster sharper than necessary Clock fall time VOS Clock fall time 1 6 1 16mV 0 4mV EECS 24
16、7 Lecture 17 Nyquist Rate ADCs Sampling 2008 H K Page 50 Switch Charge Injection Error Reduction How do we reduce the error Reduce switch size to reduce channel charge Reducing switch size increases increased distortion not a viable solution Small and small V use minimum chanel length mandated by technology For a given technology x V constant ch o s ss ONs oxGSth oxGSth s osoxHith 2 1Q V 2 C CT RC note k W 2 CVV L Consider the figure of merit FOM W CVV 1C L FOM2 VCWC L VVV FOML Li Qiang UESTC SC
