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1、NCVerilog 设计秘诀与点评 2009 年 07 月 16 日 星期四 下午 05 06 1 S 8 E K x Z This approach allows completely transparent mixed language mixed level and mixed cycle event simulations It also lays the foundation for mixed signal simulations y l3 s E q C J9 o Y4 C w c 2 External Interface 1 VHDL VHPI OMI 2 Verilog PL
2、I VPI OMI F9 z9 W1 G J y Modelsim 和 VCS 也有这个功能 PLI 用的比较多 仿真器一般自带常用的 PLI 8 s s o u a y3 k Z y 如果需要添加 FSDB 支持 需要将 debussy 提供的 libpli dll 和 libpli lib 拷贝到 tools lib 下面 Z m X9 X t E 7 Y 3 After elaboration Single executable code stream Affirma NC Simulator P J n h D 4 Code Coverage 5 Verilog supported e
3、 Y1 k f1 h j 1 OVI 2 0 3 8 t0 N0 i o 2 IEEE 1364 3 Verilog XL implementation 6 NC Verilog use Library Cell View 0 k r Z 4 cds lib This file contains statements that define your libraries and that map logical library names to physical directory paths 7 S f8 n8 L h4 j O W hdl var This file defines whi
4、ch library is the work library c3 i7 y6 e Y T F q 7 You can write a setup loc file to change the directories to search or to change the order of precedence to use when searching for the cds lib and hdl var files an elaborator called ncelab to build the model and then invokes the ncsim simulator to s
5、imulate the model Multi step invocation invoke ncvlog ncelab and ncsim separately G0 K3 k p o A The cell binding mechanism is the major difference between the two invocation methods 9 ncpack change the properties of a database to make it read only or add only E0 l p y3 9 Y inca architecture lib vers
6、ion pak inca sun4v 091 pak ncls utility list the objects contained in the library system 10 Library files protect 1 file locking mechanism ncpack unlock to unlock a file 2 signal handling mechanism ensures that any unexpected event 0 X8 i A g F S C9 P5 r J o 0 T0 q 11 cdsdoc To invoke the Cadence do
7、cumentation window 3 a e1 M k3 j x L M J tool name help nchelp options tool name message code o Q y D2 q H p6 M0 d h ncsim help help options command all command options 11 R X A l NCLaunch is a graphical user interface nclaunch 3 e Q J l3 S c O6 F V SimVision Waveform Viewer 7 e 1 i r y1 D M u Z 12
8、Many of these options have a corresponding plus option that you J 8 b o t U can use on the ncverilog command ncvlog ieee1364 ncverilog ncieee1364 4 h D J8 6 a When you run ncverilog the parser is invoked with the update option by default 2 M8 O k 15 ncverilog args in the snap nc directory command li
9、ne options of ncverilog r Q8 N D2 h6 p y1 C 所以前一次的命令在彼处有保存 g f N8 k 5 W4 3 2 J S g5 7 All tools share a common log file named ncverilog log 查看 log 文件从而掌握运行时情况是最重要的 debug 方法之一 i Y Writes the SNAPSHOT variable to the hdl var file in the snap nc directory to store the name of the snapshot used in this
10、run 3 O0 o L l J The SNAPSHOT variable in the hdl var file is used to determine what snapshot was created the last time this directory was used 16 The next time you invoke ncverilog it compares the current set of command line options to the options stored in the ncverilog args file All of the plus o
11、ptions and dash options must be the same and in the same order for the options to be evaluated as equal u6 o5 b2 r9 8 h V B4 8 G w3 x q 17 T9 N n 1 r T P2 4 O The ncverilog ncuid ncuid name option enables functionality in ncverilog that lets you run multiple simulations using the same intermediate o
12、bjects and the same storage locations The ncuid option enables this functionality by providing a unique ID name for each simulation t7 k k j S 6 0 G0 y y M y z 18 命令行参数含义 1 z2 R f0 B5 e F8 l b1 G ncverilog h all cdslib path checkargs Display a list of the arguments used on the command line m k M7 H
13、B6 i F T0 B compile Run ncvlog to compile the design but do not invoke ncelab to elaborate the design or ncsim to simulate debug Turn on read access to all objects in the design 2 y z K i V F9 Y This option is the same as ncaccess r y P X elaborate Run ncvlog and ncelab g0 C a p8 k3 a L z I expand E
14、xpand all vectors hdlvar path h J Z7 a t t3 A u G d9 x 4 n5 n import Prepare this Verilog design for import to VHDL mixedlang Search the library structure for a VHDL binding for instances that correspond to VHDL import 9 v J q a S3 D1 y H 5 n Z name name Use the specified name for the snapshot and f
15、or the INCA libs snap nc directory 0 v3 i1 h3 i6 O8 J ncelabargs string Pass the specified ncelab command options to the elaborator before invoking it 4 c1 q G8 e3 t0 Y B l0 S3 H ncelabexe path to ncelab ncerror warning code Increase the severity level of the specified warning message from warning t
16、o error 1 Q C x7 a u b7 s3 V ncfatal warning code error code Increase the severity level of the specified warning message or error message from warning or error to fatal nclibdirname directory name to change INCA libs ncls all List all of the objects in all libraries ncls dependents Show the dependents for each object h w N w C E5 v E N0 e3 S 1 g T l V9 e 1 L1 T h E x ncverilog source v ncuid test1 O f s1 r9 P r V ncverilog source v ncuid test2 Two snapshots are generated in the INCA libs workli
