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1、ESD Protection Design Seminar Jim Sutherland Senior Applications Engineer Outline 4 What is ESD 4 What damage can it cause 4 Why is the problem growing 4 What are the issues for the designer 4 How can we measure it 4 How can we protect equipment from ESD What Is ESD 4ESD Electro Static Discharge 4Ge
2、neration 4Triboelectric friction causes accumulation of charge 4Induction field induces charge 4Discharge 4Dielectric air breakdown 4Electric field increases when charged bodies approach each other 4Current flow into circuitry ESD Damage of ICs 4Permanent 4Oxide breakdown shorts opens latch up 4Temp
3、orary 4Latch up ground bounce 4Latent 4Degradation from an ESD event ESD problem is growing 4Circuits Systems 4Old Robust ICs many components large board area 4Spark gap 4Low cost low stability large board area 4Discrete Zener diodes 4High capacitance many components large board area 4Discrete PN di
4、odes 4Low capacitance many components large board area 4Integrated PN diodes Integrated Diode Networks 4Superior downstream ESD protection 4High speed response 4ESD current steered to GND or VCC 4Minimum Signal Degradation Low C 4Minimal board space weight 4Low assembly manufacturing costs 4Minimal
5、Design In Time 4Long term reliability Choosing an ESD Diode Network 4 How many lines are needed 4 How much capacitance e g 5 pF 4 What is the HBM rating e g 15 kV 4 What is the downstream clamp voltage e g 13 V 15 kV HBM pulse 4 What is the contact discharge rating e g 8 kV 4 What is the air dischar
6、ge rating e g 15 kV 4 What package e g 24 pin QSOP ESD Diode Network Placement The Need to Keep ESD Diodes Downstream of Line Inductances Also put protection diodes at most likely ESD entry point the connector Preferred Layout ESD Entry Point Parasitic L Vcc Gnd Protected Device Poor layout increase
7、d clamp voltage due to parasitic inductance Parasitic L Vcc Gnd Protected Device ESD Entry Point Designing for Minimal Power Rail Inductance Add Bypass Capacitor Place Ceramic bypass capacitor 0 1 0 2 uF as close as possible to ESD diode network power rail to shunt ESD current to both power rails Ma
8、ybe add Zener in parallel with capacitor to minimize parasitic inductance of bypass capacitor Protected Device Gnd Vcc C Using a Series Resistor to Minimize Downstream Current 4 Can be considered for latch up sensitive applications 4 Guaranteed clamping voltage limits current downstream I V R 4 Only
9、 for inputs with high Z 4 Only for output drivers with low Z 4 watch out for filtering of signal Power down Issues 4 Diode protected systems that are powered down can drain current from an active high input through the diode to VCC 4 This can drain batteries and or damage devices on the same line 4
10、To avoid this isolate VCC from the bypass capacitor with a blocking diode 4 One diode solution Component and System Specifications 4There is no simple formula to translate system specifications into component specifications 4IEC 1000 4 2 Specification is more severe than HBM 4Line capacitance and in
11、ductance shape the ESD pulse reducing its peak value 4Poor device placement can degrade performance 4If there are multiple devices on a line decide which to protect 4The relationship between downstream clamp voltage and downstream protection is not exact Validating the Design 4Define the practical l
12、imits of functional failure e g Data integrity recovery time 4Test only at those places subject to touch during normal operation 4Use Contact ES Discharges to coupling planes conductive surfaces I O pins flex pads and power pins 4Use Air ES Discharges to insulating surfaces openings at edges of keys
13、 flex cables vent areas seams slots apertures Total Solution Cost 4 ESD failure is a question of statistics 4 One cannot eliminate all reliability issues 4 Goal is to minimize total solution cost 4 Cost of reliability 4 Cost of protection 4 Must find proper minimum Lightning vs ESD 200MV 30kA 30us 15kV 45A 80nS
