《IBM硅基光子技术进展2010年》由会员分享，可在线阅读，更多相关《IBM硅基光子技术进展2010年（30页珍藏版）》请在金锄头文库上搜索。
1、 2010 IBM Corporation CMOS Integrated Silicon Nanophotonics: Enabling Technology for Exascale Computational Systems William Green Solomon Assefa Alexander Rylyakov Clint Schow Folkert Horst Yurii Vlasov Invited talk at SEMICON 2010, December 1, Tokyo Dr. Yurii A. Vlasov, Manager, Silicon Integrated
2、Nanophotonics IBM TJ Watson Research Center, Yorktown Heights, NY 2010 IBM Corporation SEMICON, December 1, 2010 Tokyo Optical Interconnects in HPCS ? IBM Petascale 1,000,000 links ? 192 GB/s Host Connection ? 336 GB/s to 7 other local nodes in the same drawer ? 240 GB/s to local-remote nodes in the
3、 same supernode (4 drawers) ? 320 GB/s to remote nodes ? 40 GB/s to general purpose I/O 4 A. Benner, IBM, OFC 2010, paper OTuH1 Avago microPODTM M. Fields, Avago, OFC 2010, paper OTuP1 http:/www.ncsa.illinois.edu/BlueWaters/ 2010 IBM Corporation SEMICON, December 1, 2010 Tokyo Silicon Integrated Nan
4、ophotonics ? An Introduction 2010 IBM Corporation SEMICON, December 1, 2010 Tokyo N parallel channels N parallel channels Goal: Integrate Ultra-dense Nanophotonics Circuits with CMOS chip Off-Chip and On-Chip Nanophotonics Interconnects Message 1Tbps aggregate BW Core 1Core N Message 1Tbps aggregate
5、 BW CMOS Serializer Electrical- to-Optical CMOS Deserializer Optical-to- Electrical CMOS Driver CMOS Amplifier Modulator WDM WDM Switches Detector 2010 IBM Corporation SEMICON, December 1, 2010 Tokyo Penetration of optics into HPCS Roadrunner Blue Waters MareNostrum HPCS Single HPC machine will cont
6、ain a similar number of optical channels as currently exist today in all parallel optical links worldwide on-boardrackback plane on-chip WW volume in 2009 Courtesy of M. Taubenblatt 2010 IBM Corporation SEMICON, December 1, 2010 Tokyo CMOS front-end monolithic Nanophotonics integration BOX Si SOI Op
7、tical waveguide FET M1 ? Nanophotonics sharing Si layer with FET body Advantages: ? Deeply scaled Nanophotonics ? Most dense integration with CMOS ? Ultra-low power optical interconnects ? Same mask set, standard processing ? Same design environment (e.g. Cadence) ? Same EDA tools and design flow ?
8、Possible in-line system-level testing 1 2 3 4 5 6 6-channel WDM 1 6 2010 IBM Corporation SEMICON, December 1, 2010 Tokyo IBM Silicon Nanophotonics Scientific Impact (2003-2010) Journal papers: 50 (including 5 Nature, 6 Invited) Conferences: 150 (including 76 Invited/Plenary) Citation index:2,100 Pat
9、ents:30 2005 Slow Light 2006 Si Modulator 2007 Optical Buffer 2008 Si Switch 2009 APD Detector 2010 Amplifier World-class scientific work laid solid foundation for novel technology development 2010 Ge Receiver 2010 IBM Corporation SEMICON, December 1, 2010 Tokyo Silicon Integrated Nanophotonics ? SN
10、IPER project at IBM Research (Silicon Nanoscale-Integrated Photonic and Electronic tRansceiver) 2010 IBM Corporation SEMICON, December 1, 2010 Tokyo IBM SNIPER Technology (2008) 2010 IBM Corporation SEMICON, December 1, 2010 Tokyo Shallow Trench Isolation Well implants/Activation Gate formation Sour
11、ce/Drain Activation Silicidation Cu back-end wiring Goal: Nanophotonics devices integrated into CMOS FEOL process (with minimal change to CMOS flow and minimal additional masks) FEOL CMOS FLOW Photonics as a new feature in standard CMOS Over 30 base patents DETECTOR MODULATOR FIBER COUPLER ?Most of
12、the mask levels and processing modules are shared ?Minimal additional photonics modules added IBM SNIPER Technology (2008) 2010 IBM Corporation SEMICON, December 1, 2010 Tokyo SNIPER project at IBM Research ? CMOS Transceiver components (after integration of all Nanophotonics modules) 2010 IBM Corpo
13、ration SEMICON, December 1, 2010 Tokyo CMOS performance: Digital circuits CMOS Ring Oscillator in 130nm CMOS GR Design Die photo 65-stage RO 10-stage divider 4-stage amplifier ?Digital CMOS Circuitry integrated with Photonics modules ?130nm design rules ?Ring oscillator with 12ps delay per stage Per
14、formance 2010 IBM Corporation SEMICON, December 1, 2010 Tokyo CMOS performance: Analog circuits Design Receiver amplifier Die photo TIA LA ?Analog CMOS Circuitry integrated with Photonics modules ?130nm design rules ?Core area 170 x40m (TIA) and 160 x50m (LA) ?28mW power consumption at 5Gbps (TIA an
15、d LA) Performance Assefa et al, JSTQE, September 2010 5Gbps open eye DC-coupled common gate TIA 7-stage limiting amplifier LA open-drain output buffer. 2010 IBM Corporation SEMICON, December 1, 2010 Tokyo CMOS performance: Analog circuits Transmitter modulator driver Design Die photo ?Analog CMOS Ci
16、rcuitry integrated with Photonics modules ?130nm design rules ?Core area 170 x60m ?36mW power consumption at 5Gbps Performance 5Gbps open eye pre-driver differential output buffer 2010 IBM Corporation SEMICON, December 1, 2010 Tokyo SNIPER project at IBM Research ?Nanophotonics Transceiver components 2010 IBM Corporation SEMICON, December 1, 2
