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1、. . .-LCD1602数字钟-Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_arith.all;Use ieee.std_logic_unsigned.all;Entity clock isPort( rst,clk : in std_logic; rs,en,rst_out,sec_out: out std_logic; rw : out std_logic; data_out : out std_logic_vector(7 downto 0); RD,WR : IN STD_LOGIC;-读写控制 DATA_O
2、 ,CONT_O : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-数据输出 DATA_I,CONT_I : IN STD_LOGIC_VECTOR(7 DOWNTO 0);-数据和地址输入 SCLK : OUT STD_LOGIC; IO : INOUT STD_LOGIC; IOB : OUT STD_LOGIC ; k1,k2 : IN STD_LOGIC); End clock;Architecture fwm of clock is TYPE states IS(hold,func_set,dis_on,mode_set,write_char1,write_ch
3、ar2,write_char3,write_char4,write_char5,write_char6, write_char7,write_char8,write_char9,write_char10,return_home,toggle_e,rst1,rst2,rst3,dis_off,dis_clr); SIGNAL state,n_state:states; SIGNAL s0,s1,m0,m1,h0,h1,t: std_logic_vector(3 downto 0); SIGNAL clk_400Hz,clk_10Hz,clk_40Hz: std_logic; SIGNAL DAT
4、A_TEMP : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL CONT_TEMP : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL SECOND : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL MINUTE : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL HOUR : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL DAY : STD_LOGIC_VECTOR(7 DOWNTO 0); CONSTANT PROCECT : STD_LOGIC_VECT
5、OR:=10001110;-保护位 CONSTANT SECOND_WRITE: STD_LOGIC_VECTOR:=10000000;CONSTANT SECOND_READ : STD_LOGIC_VECTOR:=10000001;CONSTANT MINUTE_WRITE: STD_LOGIC_VECTOR:=10000010;CONSTANT MINUTE_READ : STD_LOGIC_VECTOR:=10000011;CONSTANT HOUR_WRITE : STD_LOGIC_VECTOR:=10000100;CONSTANT HOUR_READ : STD_LOGIC_VE
6、CTOR:=10000101;CONSTANT DAY_WRITE : STD_LOGIC_VECTOR:=10000110;CONSTANT DAY_READ : STD_LOGIC_VECTOR:=10000111;-CONSTANT MONTH_WRITE : STD_LOGIC_VECTOR:=10001000;-CONSTANT MONTH_READ : STD_LOGIC_VECTOR:=10001001;-CONSTANT YEAR_WRITE : STD_LOGIC_VECTOR:=10001100;-CONSTANT YEAR_READ : STD_LOGIC_VECTOR:
7、=10001101;Begin rst_out=NOT rst; sec_out=s0(0); Process(clk,rst) -50MHz分频到400Hz variable cnt1: integer range 0 to 62500;begin if rst=0 then cnt1:=0;clk_400Hz=0; elsif clkEVENT and clk=1then if cnt162500 then cnt1:=cnt1+1; else cnt1:=0;clk_400HZ= not clk_400Hz;end if; end if;end process;process(clk_4
8、00HZ,rst)variable cnt2: integer range 0 to 199;begin if rst=0 then state=rst1;data_out=X38;n_state=rst2;en=1;rs=0;rw=0; elsif clkEVENT and clk=1 then if cnt219 then cnt2:=cnt2+1; else cnt2:=0;clk_400Hzen=1;rs=0;rw=0;data_out=X38;state=toggle_e;n_stateen=1;rs=0;rw=0;data_out=X38;state=toggle_e;n_stat
9、een=1;rs=0;rw=0;data_out=X38;state=toggle_e;n_stateen=1;rs=0;rw=0;data_out=X38;state=toggle_e;n_stateen=1;rs=0;rw=0;data_out=X08;state=toggle_e;n_stateen=1;rs=0;rw=0;data_out=X01;state=toggle_e;n_stateen=1;rs=0;rw=0;data_out=X0c;state=toggle_e;n_stateen=1;rs=0;rw=0;data_out=X06;state=toggle_e;n_stat
10、een=1;rs=1;rw=0;data_out=X3 & h1;state=toggle_e;n_stateen=1;rs=1;rw=0;data_out=X3 & h0;state=toggle_e;n_stateen=1;rs=1;rw=0;data_out=X3a;state=toggle_e;n_stateen=1;rs=1;rw=0;data_out=X3 & m1;state=toggle_e;n_stateen=1;rs=1;rw=0;data_out=X3 & m0;state=toggle_e;n_stateen=1;rs=1;rw=0;data_out=X3a;state=toggle_e;n_stateen=1;rs=1;rw=0;data_out=X3 & s1;state=toggle_e;n_stateen=1;rs=1;rw=0;data_out=X3 & s0;state=toggle_e;n_stateen=1;rs=1;rw=0;data_out=X2e;state=toggle_e;n_stateen=1;rs=1;rw=0;data_out=X3 & t;state=toggle_e;n_stateen=1;rs=0;rw=0;data_ou
