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1、 指令类型31:2625:2120:1615:1110:65:0R类型OpRsRtRdshamtfunct含义nop00000000000000000000000000000000空操作addu000000rsrtrd00000100001加（不带溢出）subu000000rsrtrd00000100011减（不带溢出）and000000rsrtrd00000100100与or000000rsrtrd00000100101或xor000000rsrtrd00000100110异或nor000000rsrtrd00000100111或非sllv000000rsrtrd00000000100逻辑左
2、移变量srlv000000rsrtrd00000000110逻辑右移变量I类型OpRsRtimmediatebltz000001rs00000Immediate小于0转移beq000100rsrtImmediate相等转移bne000101rsrtImmediate不相等转移addi001000rsrtImmediate加立即数andi001100rsrtImmediate与立即数ori001101rsrtImmediate或立即数lw100011rsrtImmediate取字sw101011rtrtImmediate存字J类型OpAddressj000010address无条件跳转综述：本设
3、计选用了如下指令，基于此设计出了单周期MIPS处理器，并在单周期的基础上添加了5级流水线设计出了带五级流水线的MIPS处理器。 第一部分 单周期MIPS处理器一、 代码 - Module Name: top_mips - Behavioral 顶层模块-library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity top_mips is port( reset: in std_logic; clk: in std_logic; ov: ou
4、t std_logic);end top_mips;architecture Behavioral of top_mips is signal s_pc:std_logic_vector(31 downto 0); -pc输入 signal s_pc_i:std_logic_vector(31 downto 0); -pc输出signal s_command:std_logic_vector(31 downto 0); -指令signal s_add1_pc:std_logic_vector(31 downto 0); -pc+1值signal s_shift:std_logic_vector
5、(27 downto 0); -指令低26位左移2位后值signal s_jump_pc:std_logic_vector(31 downto 0); -绝对跳转signal s_regdst:std_logic; -控制信号 signal s_jump: std_logic;signal s_branch: std_logic;signal s_memread: std_logic;signal s_memtoreg: std_logic;signal s_aluop: std_logic_vector( 3 downto 0);signal s_memwrite:std_logic;sig
6、nal s_alusrc:std_logic;signal s_regwrite: std_logic;signal s_opa:std_logic_vector(31 downto 0); -ALU操作数signal s_opb:std_logic_vector(31 downto 0); -ALU操作数signal s_reg_data:std_logic_vector(31 downto 0); -寄存器读出的第二个数据signal s_imm_data:std_logic_vector(31 downto 0); -低16位符号扩展后signal s_zero:std_logic; s
7、ignal s_alu_result:std_logic_vector(31 downto 0);signal s_branch_pc:std_logic_vector(31 downto 0); -条件跳转signal s_1orbranch:std_logic_vector(31 downto 0); signal s_ram_data:std_logic_vector(31 downto 0);signal s_wr_data:std_logic_vector(31 downto 0);signal s_mux:std_logic;signal s_alu_ctrl:std_logic_
8、vector(3 downto 0);signal s_aimreg_addr:std_logic_vector(4 downto 0); 写寄存器堆的地址 component pc is -pc指针模块 port( reset: in std_logic; clk: in std_logic; pc_i: in std_logic_vector(31 downto 0); pc_o:out std_logic_vector(31 downto 0); end component; component memory is -指令存储器 port( reset: in std_logic; me
9、m_adr: in std_logic_vector(31 downto 0); mem_out: out std_logic_vector(31 downto 0); end component; component reg_32bit_array is -寄存器堆 port( reset: in std_logic; clk: in std_logic; wr_en: in std_logic; addr_wr: in std_logic_vector(4 downto 0); addr1_rd: in std_logic_vector(4 downto 0); addr2_rd: in
10、std_logic_vector(4 downto 0); reg_data_i: in std_logic_vector(31 downto 0); reg_data1_o: out std_logic_vector(31 downto 0); reg_data2_o: out std_logic_vector(31 downto 0); end component; component ram is -数据存储器 port( reset :in std_logic; clk :in std_logic; rd_en :in std_logic; wr_en:in std_logic; ad
11、dr: in std_logic_vector(5 downto 0); data_i: in std_logic_vector(31 downto 0); data_o: out std_logic_vector(31 downto 0); end component; component fsm is - 指令译码器 port( command:in std_logic_vector(5 downto 0); regdst:out std_logic; jump : out std_logic; branch: out std_logic; memread: out std_logic; memtoreg: out std_logic; aluop: out std_logic_vector(3 downto 0); memwrite:out std_logic;
