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1、高级体系结构课程要点,第一章 前言 计算机技术快速法进步的原因 技术进步Moore定律发展 体系结构发展 体系结构演化过程 现代计算机体系结构的组成 高级计算机体系结构研究范畴,计算机系统结构的分类 Flynn分类法-定性 冯氏分类法-定量,第三章 Instruction-Level Parallelism and Its Dynamic Exploitation,What is pipelining? How is the pipelining Implemented? What makes pipelining hard to implement? How does CPI descend
2、 ? CPI=1 CPI1 CPI1,Ideal Performance for Pipelining Ideal speedup equal to Number of pipe stages MIPS instruction format Works in the MIPS 5 stage pipeline The MIPS pipelining Pipeline hazard: the major hurdle Structural hazards Data hazards Control hazards be resolved by Stall,Solution imaginable f
3、or Structural hazards “ double bump” Insert stall provide another memory port split instruction memory and data memory use instruction buffer fully pipelined function unit Why allow machine with structural hazard ?,Solution imaginable for Data hazards,Interlock: insert stalls Detect: Data Hazard Log
4、ic Forwarding: reduce data hazard stalls compiler to avoid load stall,Solution imaginable for Control hazards,Move the Branch Computation Forward Simple solutions Freeze or flush the pipeline Predict-not-taken (Predict-untaken) Treat every branch as not taken Predict-taken Treat every branch as take
5、n Delayed branch a,b,c Cancelling function,Extending the MIPS Pipeline to Handle,complex pipeline structure Pipelining time parameter Latency Initiation interval The out of order The new types of data hazards RAW Stalls arising WAW,Instruction-Level Parallelism,CPIpipelined = Ideal pipeline CPI+ pip
6、elined stall cycles per instruction =1+ Structual stalls + RAW stalls + WAR stalls + WAW stalls + Control stalls Basic Block ILP is quite small Data Dependence and Hazards True Data Dependence RAW( Read after write) Name dependence Anti-dependence WAR( Write after read) Output dependence WAW(Write a
7、fter write),Some Property about,Dependences are a property of programs hazard or length of any stall is a property of the pipeline (hardware) Control Dependencies Branch Behavior,Overcoming Data Hazards with Dynamic Scheduling,Key idea: Allow instructions behind stall to proceed in-order issue out-o
8、f-order execution out-of-order completion,Dynamic Scheduling with a Scoreboard,Issue: a instruction is issued when The functional unit is available and No other active instruction has the same destination register. Avoid strutural hazard and WAW hazard Read Operands (RD) The read operation is delaye
9、d until the operands are available. This means that no previously issued but ncompleted instruction has the operand as its destination. This resolves RAW hazards dynamically Execution (EX) Notify the scoreboard when completed so the functional unit can be reused. Write result (WB) The scoreboard che
10、cks for WAR hazards and stalls the completing instruction if necessary.,Dynamic Scheduling with Tomasulos Algorithm(renaming in hardware! ),Control avoids WAR, WAW hazards Results to FU from RS not through registers, over Common Data Bus that broadcasts results to all FUs,Three Stages of Tomasulo Al
11、gorithm,Issueget instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr mark reservation station available,Reservation Station Components,Reservation station: Op: Operation to perform in the unit Vj, Vk: Value of Source operands Store buffers has V fiel
12、d, result to be stored Qj, Qk: Reservation stations producing source registers (value to be written) Note: Qj,Qk=0 = ready Store buffers only have Qi for RS producing result A: hold info. for memory address calculation Busy: Indicates reservation station or FU is bus Register result statusIndicates
13、which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register.,Reducing Branch Costs with Dynamic Hardware Prediction(3.4),1-bit Branch-Prediction Buffer 2-bit Branch-Prediction Buffer Correlating Branch Prediction Buffer Tournament B
14、ranch Predictor Branch Target Buffer Trace Cache,Hardware-Based Speculation (3.7),基本概念：基于硬件的投机技术实质上是综合了下述三种技术的一种集成技术，它们是： 应用动态转移预测技术选择投机指令； 应用投机技术达到在控制相关性消除以前就执行投机指令； 应用动态调度技术来调度程序基本块的不同组合。,基于Tomasulo动态调度的硬件投机,乱序执行 按序结束 增加流水级：Commit（交付，或提交） 增加流水部件：Reorder Buffer Reorder buffer的作用,硬件投机指令执行四个节拍的功能,Iss
15、ue in order Execute out of order Write result out of order Commit-in order,指令多发射技术,一个时钟周期里发射多条指令，即指令的多发射技术。 多发射技术的两种方法(Two basic flavors)： superscalar(超标量）方法 VLIW(超长指令字）方法,Scheduled,Superscalar processor has dynamic issue capability, VLIW processor has static issue capability,双发射Tomasulo流水线,7,Multip
16、le Issue with Speculation(without speculation),Multiple Issue with Speculation(with speculation),8,14,19,第四章 Exploiting Instruction Level Parallelism with Software Approaches,Loop Unrolling Using Loop Unrolling and Pipeline Scheduling with Static Multiple Issue,Static Multiple Issue: the VLIW Approach,相关性的几个概念 loop-carried dependence循环传递相关- Data accesses in later iterations are dependent on data values produced in earlier iterations Dependence di
