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1、2014年福建省大学生合泰杯单片机应用设计竞赛 竞赛培训会Holtek HT32F1765(March 2014),2,Agenda,ARM Cortex-M3,4,Cortex-M Series,Source : ARM,5,Overview ARM Cortex-M3,Cortex-M3 CoreThumb & Thumb2 decoders32-bit ALUHardware divider & MultiplierETM, NVIC, and Bus InterfaceCortex-M3 ProcessorNested Vectored Interrupt Controller (NV
2、IC)Optional Memory Protection Unit (MPU) (Not available in HT32F125x)Bus matrixCode / SRAM / Peripheral interfacesDebug componentsOptional Embedded Trace Macrocell (ETM) (Not available in HT32 Series),Source : ARM,6,Architecture,* HT32F2755 only,3 Independent Bus ICode, DCode, System,7,1.25 DMIPS,0.
3、90,0.93,0.75,Performance,50MHz CM3 = 1.25 x 50 = 62.5 DMIPS50MHz CM0 = 0.90 x 50 = 45.0 DMIPSPerformance = (62.5-45)/45 = 38.9%,Source : ARM,8,Advantages,Source : ARM,9,ARM Cortex-M3,Programmers ModelMemory ModelException ModelFault HandlingPower ManagementCortex-M3 Peripherals,10,Programmers Model
4、Register,11,Programmers Model Operation Mode,12,Memory Model Memory Map,4 GBFixed mapSimplifies softwareBit Band,13,Memory Model Bus Interface,Source : ARM,14,Exception Model,1 15 for system, 16 255 for IP, Programmable priorityVector table contains address of ISRInterrupt Service RoutineDefault at
5、address 0x0 after resetRe-locatable by NVIC VTO register,15,Fault Handling,Faults are a subset of exceptions,Deal with FaultsDevelopment: DebugProduct: Reset / Fault recovery / Task termination,16,Power Management,Power saving modeSleep mode: Stops the processor clockDeep sleep mode: SLEEPDEEP signa
6、l for clock gating of all systemEntering power saving modeSleep modeWait For Interrupt (WFI) instruction Wait For Event (WFE) instructionDeep Sleep modeWFI or WFE with SLEEPDEEP bit in System Control Register (SCR)Sleep-on-exitSLEEPONEXIT bit in SCRWakeup from sleep modeWFI: Active interruptWFE: Act
7、ive interrupt, External event, Pending interrupt,17,Cortex-M3 Peripherals,Nested Vectored Interrupt Controller (NVIC)System Control Block (SCB)System Timer, SysTickDebug Support,18,Nested Vectored Interrupt ControllerLow interrupt latencyTypical as low as 12 6 CyclesUp to 240 interruptUp to 256 prio
8、rity levelsHandler mode / Privileged levelRegistersInterrupt Set-Enable RegisterInterrupt Clear-Enable RegisterInterrupt Set-Pending RegisterInterrupt Clear-Pending RegisterActive Bit RegisterInterrupt priority Register,Cortex-M3 Peripherals - NVIC,19,Cortex-M3 Peripherals - SCB,20,Cortex-M3 Periphe
9、rals SysTick,24-bit self-reloading down counterFor RTOS tick timer or simple counterClock Source: Core clock External reference clockException vector: #15, SysTickAccessible from Privileged level4 RegistersSYST_CSR: COUNTFLAG / CLKSOURCE / TICKINT / ENABLESYST_RVR: RELOADSYST_CVR: CURRENTSYST_CALIB:
10、 NOREF / SKEW / TENMS,21,Cortex-M3 Peripherals Debug Support,Core Debug Halting / Single StepRegister Access (R0R12, SP, LR, PC, etc.)Debug ExceptionSystem Debug Components,22,Cortex-M3 Peripherals Debug Support,Debug Access Port (DAP)AHB-APSW-DP / SWJ-DP,23,Cortex-M3 Reference,Cortex-M3 Devices Gen
11、eric User GuideThe Definitive Guide to the ARM Cortex-M3Cortex-M3 Technical Reference ManualARMv7-M Architecture Reference Manual,Holtek HT32F1765Peripherals,25,HT32F1755 / 1765 / 2755,ArchitectureHT32F1755HT32F1765HT32F2755,26,CPU CoreOperating Voltage System Clock,JTAG / Serial Wire DebugMax. gene
12、rated from HSE / HSI by PLL,FlashSRAM,Flash Security / AcceleratorHT32F1755 : 32KB HT32F1765 / 2755 : 64KB,Oscillators,HSE : 4MHz 16MHz (Clock Stop Detection )HSI : 8MHz 5% -40C +85CLSE : 32.768KHzLSI : 32KHz 10% 25C,PDMAUSBSCI,12 channelsUSB 2.0 Full Speed DeviceISO7816-3 Smart Card Interface,Corte
13、x-M3 r2p0 2.7V 3.6V72MHz,128K Bytes32K / 64K Bytes,High-Speed ExternalHigh-Speed Internal RCLow-Speed ExternalLow-Speed Internal RC,111,CSIF*,CMOS sensor interface, Clock up to 24MHzYUV or RAW RGB data format (QVGA / CIF)* For HT32F2755 only,1,Function,Description,Spec / Number,HT32F1755/1765/2755 F
14、eature (1/3),27,Basic Function Timer(BFTM) General Purpose Timer(GPTM) Motor Control Timer(MCTM), 32-bit compare counter One shot / Repetitive interrupt mode Input capture Output compare PWM generation (Edge and Centre-aligned mode) One Pulse Mode output QEI & Hall sensor interfaceAs GPTM but with e
15、xtra motor functions: Complementary output with programmable dead time insertion Programmable polarity Programmable idle state Break protection Support 3-phase motor control,USARTSPII2C,With FIFO, Baud Rate up to 4.5MbpsMaster Up to 36MHz / Slave Up to 18MHzMaster/Slave Standard/Fast mode (100 / 400
16、kHz),ADCOp Amp / ComparatorRTCWatchdog,Max. 1 Msps with 12-bit SAR ADC,221,222,12-bit8 channels211,Function,Description,Spec / Number,HT32F1755/1765/2755 Feature (2/3),28,LVDBODPORInternal LDO,4 levels : 2.7V 3.0V, 0.1V per levelBrown Out Detector voltage : 2.6VPower On Reset : 1.36VVIN = 2.7V 3.6VNormal mode : VOUT = 1.8V / 200mALow-power mode : VOUT = 1.8V / 100mA,
