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1、1,第6章,VHDL顺序语句,2,library ieee; use ieee.std_logic_1164.all; entity reset_dff2 is port( clk,reset : in std_logic; d : in std_logic; q : out std_logic); end reset_dff2; architecture rtl of reset_dff2 is begin process begin wait on clk, reset; if (reset = 1 ) then q = 0; elsif（clkevent and clk=1) then
2、q = d; end if; wait on clk, reset; end process; end rtl;,3,process begin wait until clkevent and clk=1； if (reset = 1 ) then q = 0; else q = d; end if; end process; end rtl;,4,library ieee; use ieee.std_logic_1164.all; entity clk_generator is port( clk : out std_logic); end clk_generator; architectu
3、re example of clk_generator is begin process begin wait for 125 ns; clk = 0; wait for 125 ns; clk = 1; end process; end rtl;,4M时钟 发生器,5,architecture behave of example is signal a,b : std_logic; begin a = 0; label1: process begin wait until b = 1; a = 1 after 10 ns; wait until b = 0; a = 0 after 10 n
4、s; end process; label2: process begin wait until a = 0; b = 0 after 10 ns; wait until a = 1; b = 1 after 10 ns; end process; end behave;,wait until ( b=1) for 1 s,6,library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder is port( q1, q2 : in std_logic_vector(7 downto
5、 0); cs : in std_logic; q : out std_logic_vector(7 downto 0); end adder; architecture behave of adder is begin process(cs) begin if ( cs = 1 ） then q = q1 + q2; end if; end process; end behave;,使能控制端,7,entity mux2 is port( d0, d1 : in std_logic_vector(3 downto 0); sel : in std_logic; q : out std_log
6、ic_vector(3 downto 0); end mux2; architecture rtl of mux2 is begin process(d0,d1,sel) begin if ( sel = 1 ） then q = d0; else q = d1; end if; end process; end rtl;,选通控制端（二选一）,8,process(d0,d1,d2,d3,sel) begin if ( sel = “00” ）then q = d0; elsif ( sel = “01” ) then q = d1; elsif ( sel = “10” ) then q =
7、 d2; else q = d3; end if; end process;,选通控制端（四选一）,9,library ieee; use ieee.std_logic_1164.all; entity se7 is port( input : in std_logic_vector(3 downto 0); output : out std_logic_vector(6 downto 0); end se7; architecture se7_arc of se7 is begin process(input) begin case语句； end process; end se7_arc;,
8、10,case input is when “0000” = output output output output output output output output output output output output output output output output output = (0,0,0,0,0,0,0); end case;,11,entity vector_to_int is port( input : in std_logic_vector(7 downto 0); flag : out boolean; q : out integer); end vecto
9、r_to_int; architecture behave of vector_to_int is begin process(input) variable tmp : integer :=0; begin flag = false; for i in 7 downto 0 loop tmp := tmp*2; if ( input(i) = 1) then tmp := tmp +1; elsif ( input(i) /=0 ) then flag = true; end if; end loop; q = tmp; end process; end behave;,12,entity
10、logic_and is port( input : in std_logic_vector(7 downto 0); q : out std_logic); end logic_and; architecture behave of logic_and is begin process(input) variable tmp : std_logic; variable i : integer; begin tmp := 1; i := 0; while ( i 8 ） loop tmp := tmp and input(i); i := i +1; end loop; q = tmp; en
11、d process; end behave;,13,entity logic_and is port( a, b, mask : in std_logic_vector(7 downto 0); q : out std_logic_vector(7 downto 0); end logic_and; architecture behave of logic_and is begin process(a, b, mask) begin for i in 7 downto 0 loop if ( mask(i) = 1 ) then next; end if; q(i) = a(i) and b(
12、i); end loop; end process; end behave;,14,entity example is port( a, b, mask : in integer; q : out integer); end example; architecture behave of example is begin process(a, b) function maximum (a, b: integer ) return integer is variable temp : integer; begin if ( a b ) then temp := a; else temp := b
13、; end if; return(temp); end maximum; begin q = maximum( a, b ); end process; end behave;,函数返回值,15,entity mux4 is port( d0, d1, d2, d3 : in std_logic_vector(7 downto 0); s0, s1 : in std_logic; q : out std_logic_vector(7 downto 0); end mux4; architecture behave of mux4 is begin process(d0, d1, d2, d3,
14、 s0, s1) variable temp : integer; begin temp := 0; if ( s0 = 1 ) then temp := temp + 1; end if; if ( s01 = 1 ) then temp := temp + 2; end if;,case temp is when 0 = q q q q null; end case; end process; end behave;,16,entity max is port( int1, int2, int3 : in std_logic_vector(7 downto 0); q : out std_
15、logic_vector(7 downto 0); end max; architecture behave of max is procedure maximum( a, b : in std_logic_vector; c : out std_logic_vector) is variable temp : std_logic_vector(arange); begin if ( a b ) then temp := a; else temp := b; end if; c := temp; end maximum;,17,begin process(int1,int2,int3); va
16、riabltmp1,tmp2: std_logic_vector(7 downto 0); begin maximum(int1,int2,tmp1); maximum(tmp1,int3,tmp2); q = tmp2; end process; end behave;,18,entity rsff is port( s, r : in bit; q,qb : out bit); End rsff; architecture behave of rsff is begin process(s,r) variable last_state := bit; begin if ( s = 0 and r = 0 ) then last_state := last _state; elsif( s = 0 and r = 1) then last_state :=
