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1、Semiconductor Technology Trends & SMICs R&D to Supply Manufacturing Technologies,Dr. Shiuh-Wuu Lee 李序武博士 Executive VP, Technology R & D, SMIC Oct 23th, 2014,2014北京微电子国际研讨会,Safe Harbor Statements Under the Private Securities Litigation Reform Act of 1995,This document contains, in addition to histori
2、cal information, “forward-looking statements” within the meaning of the “safe harbor” provisions of the U.S. Private Securities Litigation Reform Act of 1995. These forward-looking statements are based on SMICs current assumptions, expectations and projections about future events. SMIC uses words li
3、ke “believe,” “anticipate,” “intend,” “estimate,” “expect,” “project” and similar expressions to identify forward looking statements, although not all forward-looking statements contain these words. These forward-looking statements are necessarily estimates reflecting the best judgment of SMICs seni
4、or management and involve significant risks, both known and unknown, uncertainties and other factors that may cause SMICs actual performance, financial condition or results of operations to be materially different from those suggested by the forward-looking statements including, among others, risks
5、associated with cyclicality and market conditions in the semiconductor industry, intense competition, timely wafer acceptance by SMICs customers, timely introduction of new technologies, SMICs ability to ramp new products into volume, supply and demand for semiconductor foundry services, industry ov
6、ercapacity, shortages in equipment, components and raw materials, availability of manufacturing capacity, financial stability in end markets and intensive intellectual property litigation in high tech industry. In addition to the information contained in this document, you should also consider the i
7、nformation contained in our other filings with the SEC, including our annual report on Form 20-F filed with the SEC on April 14, 2014, especially in the “Risk Factors” section and such other documents that we may file with the SEC or SEHK from time to time, including on Form 6-K. Other unknown or un
8、predictable factors also could have material adverse effects on our future results, performance or achievements. In light of these risks, uncertainties, assumptions and factors, the forward-looking events discussed in this document may not occur. You are cautioned not to place undue reliance on thes
9、e forward-looking statements, which speak only as of the date stated or, if no date is stated, as of the date of this document.,2,Outline,Major Technology Challenges SMICs Technology R&D Strategies and Plans Continue to build & enhance high quality and innovative R&D at SMIC Place significant focus
10、on leading-edge differentiation technologies Strengthen R&D on advanced CMOS technology Enrich design IP to actively support design houses for faster TTM Actively drive the growth in domestic IC industry chain 3. Concluding Remarks,3,国际主流逻辑技术路线图,1H13,2H13,1H14,2H14,1H15,2H15,2H12,1H16,2H16,1H17,2H17
11、,Skip 20nm Planar,14nm FF,16nm FF,14nm FF,14nm FF,14nm FF,22nm FF,Speculated,14nm FF,Foundry,T,GF,U,Samsung,(Intel),国际主流公司未来五年逻辑技术路线图，各公司均加快了科研进度，多数公司在未来五年均拟推出3代或3代以上技术产品。,20nm Planar,20nm Planar,10nm FinFET,10nm FinFET,10nm FinFET,10nm FinFET,7nm FinFET,7nm FinFET,7nm FinFET,7nm FinFET,Pre-manufact
12、ure Technologies,Manufacture Technologies,4,我国集成电路产业技术进步,落后2-3年,摘自：北京大学王阳元, 2012,5,光刻技术 新材料 工艺误差 新结构 工艺集成,芯片制造技术中的五大技术挑战,6,技术挑战-1: 精密图形转换,?,如何用193纳米波长光源形成65-20纳米特征长度的图形?,1.光学修正(OPC),相移掩膜(Phase Shift Mask) 2.浸没式光刻(Immersion Litho) 3.多重曝光和刻蚀(Multiple Patterning),7,光刻技术的瓶颈三因素,Phase Shift Mask Off-axis
13、illumination .,8,光学修正技术使得图形比波长短,9,Design Rule of Critical Layers,Contact PL Pitch,Fin,193nm Happy Days,193nm 光刻的瓶颈,193纳米光刻技术支撑CMOS发展65-14nm,10,新材料在CMOS中的应用,本世纪来: 47种新材料进入 集成电路制造. 共计64种材料.,12 5 47,技术挑战-2: 新材料新工艺,11,新材料技术带来的器件性能提高,0.13um 90nm 65nm 45nm 32nm,12,产品技术杀手: 工艺随机误差,技术挑战-3: 工艺误差,DFM： 研究工艺误差带来
14、的器件产品性能变化，并提出解决方案。 APC: 及时发现工艺异常.,13,Direct impact: SRAM yield Circuit performance and design margin Indirect impact: Reliability Mobility Manufacturing control,挑战：在低电压下获得高电流和少泄漏 即在低电源电压情况下（低电压可以获得好的功耗指标），要设法获得更大的驱动能力和更小的晶体管延时（提高性能）。显然，在传统的体硅平面器件上，已很难实现上述要求。,栅泄漏电流,寄生电阻,短沟效应,迁移率退化,波动性,动态功耗,驱动能力： IDSa
15、t=CgvinjCg(Vdd-Vt)eff,功耗： P=CgVdd2f+IleakageVdd,速度： g=CgVdd/IDSat,来源：北京大学黎明研究员,体硅平面工艺似乎走到尽头?,技术挑战-4: 新结构,14,3维晶体管FinFET,新器件的设计问题 新一代FinFET器件的结构优化 应力分布模拟、迁移率提取、输运机制、可靠性与涨落特性 器件结构参数和工艺参数对电路性能的影响 可制造性问题 栅泄漏电流，功函数调节，源漏串联电阻及接触电阻等关键问题 材料体系与工艺技术的稳定性可靠性问题 大生产平台上工艺集成问题 自对准多次曝光技术，纳米级Fin和Gate的光刻和刻蚀，节距的缩小带来的原子水
16、平的间隙填充，低介电常数侧墙，超低K铜互连等。,15,800,1000,1400,65nm,45nm,20nm,65-14纳米CMOS工艺流程复杂度,技术挑战-5:工艺集成技术,每一代新技术需要约20%以上的工艺设备添置和更新 几乎每步工艺需要实验,关键工艺需要数百次,1200,32nm,1600,14nm,16,Outline,Major Technology Challenges SMICs Technology R&D Strategies and Plans Continue to build & enhance high quality and innovative R&D at SMIC Place significant focus on leading-edge differentiation technologies Strengthen R&D on advanced CMOS technology Enrich desig
