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1、1 MX25L25635E P/N: PM1532REV. 0.01, NOV. 18, 2009 MX25L25635E HIGH PERFORMANCE SERIAL FLASH SPECIFICATION 2 MX25L25635E P/N: PM1532REV. 0.01, NOV. 18, 2009 Contents FEATURES 5 GENERAL DESCRIPTION .7 Table 1. Additional Features 7 PIN CONFIGURATION 8 PIN DESCRIPTION 8 BLOCK DIAGRAM .9 DATA PROTECTION
2、 10 Table 2. Protected Area Sizes 11 Table 3. 4K-bit Secured OTP Definition 11 Memory Organization .12 Table 4. Memory Organization 12 DEVICE OPERATION 13 Figure 1. Serial Modes Supported (for Normal Serial mode) .13 HOLD FEATURES .14 Figure 2. Hold Condition Operation .14 COMMAND DESCRIPTION .15 Ta
3、ble 5. Command Sets .15 (1) Write Enable (WREN) .17 (2) Write Disable (WRDI) 17 (3) Read Identification (RDID) 17 (4) Read Status Register (RDSR) 18 (5) Write Status Register (WRSR) 19 Protection Modes .19 (6) Enter 4-byte mode (EN4B)20 (7) Exit 4-byte mode (EX4B) 20 (8) Read Data Bytes (READ) .20 (
4、9) Read Data Bytes at Higher Speed (FAST_READ) .20 (10) 2 x I/O Read Mode (2READ) 21 (11) 4 x I/O Read Mode (4READ) .21 (12) Sector Erase (SE) .22 (13) Block Erase (BE).22 (14) Block Erase (BE32K) 22 (15) Chip Erase (CE) 23 (16) Page Program (PP).23 (17) 4 x I/O Page Program (4PP) .24 Program/Erase
5、Flow(1) - verify by reading array data .25 Program/Erase Flow(2) - verify by reading program/erase fail flag bit .26 (18) Continuously program mode (CP mode) 27 (19) Parallel Mode (Highly recommended for production throughputs increasing) 27 (20) Deep Power-down (DP) 28 (21) Release from Deep Power-
6、down (RDP), Read Electronic Signature (RES) 28 (22) Read Electronic Manufacturer ID 0.5s(typ.) /block (32K-byte per block); 0.7s(typ.) /block (64K-byte per block); 160s(typ.) /chip Low Power Consumption - Low active read current: 45mA(max.) at 80MHz, 40mA(max.) at 70MHz and 30mA(max.) at 50MHz - Low
7、 active programming current: 25mA (max.) - Low active erase current: 25mA (max.) - Standby current: 200uA (max.) - Deep power down current: 80uA (max.) Typical 100,000 erase/program cycles SOFTWARE FEATURES Input Data Format - 1-byte Command code Advanced Security Features - BP0-BP3 block group prot
8、ect - Flexible individual block protect when OTP WPSEL=1 6 MX25L25635E P/N: PM1532REV. 0.01, NOV. 18, 2009 - Additional 4K bits secured OTP for unique identifier Auto Erase and Auto Program Algorithms - Automatically erases and verifies data at selected sector - Automatically programs and verifies d
9、ata at selected page by an internal algorithm that automatically times the program pulse width (Any page to be programed should have page in the erased state first.) Status Register Feature Electronic Identification - JEDEC 1-byte Manufacturer ID and 2-byte Device ID - RES command for 1-byte Device
10、ID - Both REMS,REMS2, REMS4 commands for 1-byte Manufacturer ID and 1-byte Device ID Support Discoverable Memory Capabilities (DMC) signature HARDWARE FEATURES SCLK Input - Serial clock input SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode SO/SIO1/PO7 - Seri
11、al Data Output or Serial Data Input/Output for 2 x I/O mode and 4 x I/O mode or Parallel Data WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O mode HOLD#/SIO3 - HOLD# pin or serial data Input/Output for 4 x I/O mode, an internal weak pull up on the pin PO0PO6 - For parall
12、el mode data PACKAGE - 16-pin SOP (300mil) - All Pb-free devices are RoHS Compliant 7 MX25L25635E P/N: PM1532REV. 0.01, NOV. 18, 2009 Table 1. Additional Features GENERAL DESCRIPTION MX25L25635E is 268,435,456 bits serial Flash memory, which is configured as 33,554,432 x 8 internally. When it is in
13、two or four I/O mode, the structure becomes 134,217,728 bits x 2 or 67,108,864 bits x 4. The MX25L25635E features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data
14、 output (SO). Serial access to the device is enabled by CS# input. MX25L25635E, MXSMIOTM (Serial Multi I/O) flash memory, provides sequential read operation on whole chip and multi-I/O features. When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits in
15、put and data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data Input/Output. Parallel mode is also provided in this device. It features 8 bit input/output for increasing throughputs. T
16、his feature is recommeded to be used for factory production purpose. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for Continuously Program mode, and erase command is executes on sector (4K-byte), block (32K-byte/64K-byte), or whole chip basis. To provide us
