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1、Product Folder Sample when low the TDC1000 is in SLEEP mode) TRIGGER16ITrigger input RESET17IReset (active high) SCLK18ISerial clock for the SPI interface CSB19IChip select for the SPI interface (active low) SDI20ISerial data input for the SPI interface SDO21OSerial data output for the SPI interface
2、 VIO22PPositive I/O supply VDD(2)23, 24PPositive supply; all VDD supply pins must be connected to the supply. CLKIN25IClock input GND26GNegative supply (1)G = Ground, I = Input, O = Output, P = Power (2)Place a 100-nF bypass capacitor to ground in closest proximity of the pin Copyright 20142015, Tex
3、as Instruments Incorporated3 TDC1000,TDC1000-Q1 ZHCSD54B OCTOBER 2014REVISED AUGUST Pin Functions (continued) PIN TYPE(1)DESCRIPTION NAMENO. TX227OTransmit output 2 TX128OTransmit output 1 6Specifications 6.1Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted)
4、(1)(2) MINMAXUNIT VDDAnalog supply voltage, VDD pins0.36.0V VIOI/O supply voltage (VIOmust always be lower than or equal to VDDsupply)0.36.0V VIVoltage on any analog input pin(3)0.3VDD+ 0.3V VIVoltage on any digital input pin(3)0.3VIO+ 0.3V IIInput current at any pin5mA TJOperating junction temperat
5、ure40125C TstgStorage temperature range65150C (1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Re
6、commended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2)All voltages are with respect to ground, unless otherwise specified. (3)When the input voltage at a pin exceeds the power supplies, the current at that pin must not ex
7、ceed 5 mA and the voltage (VI) at that pin must not exceed 6.0 V. 6.2ESD Ratings VALUEUNIT Human-body model (HBM), per AEC A100-002(1)2000 All pins500 V(ESD)Electrostatic dischargeV Charged-device model (CDM), per AEC Corner pins (1, 14, 15 Q100-011 750 and 28) (1)AEC Q100-002 indicates HBM stressin
8、g is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted) MINMAXUNIT VDDAnalog supply voltage, VDD pins2.75.5V VIODigital supply voltage, (VIOmust always be lower than or equal to VDDs
9、upply)1.8VDDV VIVoltage on any analog input pinGNDVDDV VIVoltage on any digital input pinGNDVIOV CLKINOperating frequency0.0616MHz TJOperating junction temperature40125C 4Copyright 20142015, Texas Instruments Incorporated TDC1000,TDC1000-Q1 ZHCSD54B OCTOBER 2014REVISED AUGUST 2015 6.4Thermal Informa
10、tion(1) TDC1000 THERMAL METRICTSSOPUNIT (28 PINS) PW RJAJunction-to-ambient thermal resistance83.5 RJC(top)Junction-to-case (top) thermal resistance29.9 RJBJunction-to-board thermal resistance40.8C/W JTJunction-to-top characterization parameter2.4 JBJunction-to-board characterization parameter40.3 (
11、1)For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright 20142015, Texas Instruments Incorporated5 TDC1000,TDC1000-Q1 ZHCSD54B OCTOBER 2014REVISED AUGUST 6.5Electrical Characteristics The electrical ratings specified
12、in this section apply to all specifications in this document, unless otherwise noted. These specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of the product containing it. TA= 25C, VDD= VIO= 3.7 V, VCOM= VCM= VDD/ 2, CVCO
13、M= 10 nF (unless otherwise noted). PARAMETERTEST CONDITIONSMINTYPMAXUNIT TRANSMITTER SIGNAL PATH (TX) HIGHVDD 0.32V VOUT(TX)Output voltage swingout= 1 MHz, RL= 75 to VCM LOW0.32V IOUT(TX)Output drive currentout= 1 MHz, RL= 75 to VCM22mARMS CLKIN= 8 MHz, divide-by-2 (programmable; OUT(TX)Output TX fr
14、equency4MHz see Transmitter Signal Path) RECEIVER SIGNAL PATH (RX) LNA capacitive feedback, GPGA= 6 dB, IN= 1 STOP cycle-to-cycle tSTOPMHz, VIN= 100 mVPP, CVCOM= 1 F and50psRMS jitter Figure 14 LNA Capacitive feedback, CIN= 300 pF, IN= 1 GLNALNA gain20dB MHz, RL= 100 k to VCM, CVCOM= 1 F LNA input r
15、eferredCapacitive feedback, CIN= 300 pF, = 1 MHz, enLNA2nV/Hz noise densityVDD= 3.1 V, VIN= VCM, RL= , CVCOM= 1 F HIGHVCM+ (VCM 0.24) / (GLNA)V Resistive feedback, RL= 1 k to VIN(LNA)Input voltage range VCM, CVCOM= 1 F LOWVCM (VCM 0.24) / (GLNA)V HIGHVDD 0.24V Resistive feedback, RL= 1 k to VOUT(LNA
16、)Output voltage range VCM, CVCOM= 1 F LOWGND + 0.24V Resistive feedback, RL= 1 k to VCM, 100mV SRLNASlew rate(1)9V/s step, CVCOM= 1 F Capacitive feedback, = 1 MHz, RL= 100 k XTKMUX ch-to-ch crosstalk57dB to VCM, CVCOM= 1 F Capacitive feedback, CIN= 300 pF, RL= 100 k BWLNA3-dB bandwidth5MHz to VCM, CVCOM= 1 F LNA input offset VOS(LNA)Resistive mode, VIN= VCM, RL= 320V voltage VCOM VCOMVCOM output voltageVCMV CVCOM=
