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1、I C P l a t f o r m A-PDF Watermark DEMO: Purchase from www.A-PDF.com to remove the watermark Fan-Out WLP technology emerging on both 200mm/300mm infrastructures Infineon eWLB: the first FO-WLP wafers are mass produced at Infineon, STATS ChipPAC and ASE since 2009. Other OSATsuch as SPIL, Amkor, UTA
2、C, ACET, NANIUM, etc. are ramping Embedded die package technology to expand fast from niche to high volume markets Cost effective, small form factor, small electrical overhead, low and high density capable FOWLP vs. chip embedding: Competing technologies and infrastructures? Today, embedded die and
3、Fan-Out WLP technologies are not competing: The chip embedding technology is looking for re-placement of low cost, low pin-counts WLCSP/SOT/QFN/LGA family package applications; while FOWLP technology is rather targeting the direct replacement of higher I/Os ( 120 pins) BGA package applications Howev
4、er, in the long term, with standardization and through further technology improvements towards higher yield, fan-out WLP and embedded die technology could seriously compete in the fast growing 3D packaging market space as they will both enable the construction of ever more complex, larger SiP module
5、s cost effectively So, fan-out WLP and chip embedding into PCB laminates are just two additional key pieces of the widening tool-box for 3D packaging! I C P l a t f o r m A bump-less, wire bond-less, “substrate-less” package. It is a package with die embedded in substrate/mold/metal. Advantage SFF M
6、ulti-die integration compatible 3 Could be PP (+ Cu foil), or ABF-like material, or metal plate Die Could be PP, or ABF-like materialABF-like material I C P l a t f o r m Low-cost wafer level fan-out package structure based on the use of a metal plate with a die attached Redistribution layer is base
7、d on PCB technology Process flow: Die mounting on Cu base Embedded die in resin Via formation Seed layer formation Photoresist coating Patterning Metal plating Resist removal Seed layer etching Solder resist layer formation Solder ball attach (panel level) Singulation by saw Source: J-Devices. I C P
8、 l a t f o r m 5 4 7 mm 4 7 mm DC-DC convertor Required wafer RDL Line / space = 20/20 30/30 um Laser via / land = 70/130 um PMIC (power management IC) Required wafer RDL Same design rule as left 4 7 mm 4 7 mm Cu plate I C P l a t f o r m 6 I C P l a t f o r m I C P l a t f o r m Panel Size: 510 x 4
9、10 mm (209,100mm2) Strip Size: 240 x 76.2 mm (X2L) PKG Size: 6.28 x 4.68 mm Strip Array: 34x13 = 442 each Pkg/Per/Panel : 4,420 each Wafer size : 300mm(70,686mm2) Unit(die) size : 6.28X4.68mm Die/Per/Wafer: 2,130 each FC Cu Pillar aS3-Plus Panel vs Wafer Utilization 3:1 Area No Wafer Fab investment
10、needed, ASE uses standard FlipChip Packaging 2:1 Pkgs Source: ASE. I C P l a t f o r m Yole I C P l a t f o r m Wafer Level Fan Out Panel Level Fan Out Copper Pillar FCCSP Cu Column Via - C2iM Chip first/lastChip first/midChip lastChip last Interconnection: Via interconnect Interconnection: Via inte
11、rconnect Interconnection: Flip chip bond Interconnection: Flip chip bond 12” wafer18”x24” panel20”x20” panel21”x24” panel Wafer Fab-likePCB-likePCB-likePCB-like Pros: Fine Line/ Space Thin package Pros: Batch process Capacity Pros: Capacity Die savings Thermal Pros: Capacity Die savings Thermal, thi
12、n Cons: Capacity Yield Cons: Yield Cons: Substrate thickness Thermal Cons: Thin substrate handle I C P l a t f o r m 11 Die-firstDie-middleDie-Last DescriptionDie placement first, then RDLs 1stlayer RDL first, followed by die placement and molding, then subsequent RDLs Cu-pillar FCBGA; Cu-pillar + E
13、PP; standard FCBGA. Standard substrate and assembly process flow Pros-Simplest structure -Simplest process -Lowest process cost - Better registration - Better fine line capability for 1stRDL - Lower die loss - Conventional and mature - Minimum die loss Cons- Worse registration - Limited fine line ca
14、pability for 1stRDL - High die loss -Complex process -Higher process cost - Higher cost I C P l a t f o r m What size panel is feasible? Assembly of die on panel Die placement accuracy may be more difficult to control with large panels Large area bonders may be required Throughput (time required to
15、pick and place die in panel) How is placement accuracy impacted by tape and mold compound? What level of inspection is required to verify accuracy? What speed? Dielectric dispense methods? Spin coat? Other methods? How to control run-out at edge? Need inspection for even coating? Molding materials a
16、nd process? Panel warpage Warpageincreases with panel size Impact of materials (mold compound and filler) What type of inspection is requires and how will it work with warped panels Via formation method (minimum via diameter) Via alignment Metal plating Metal to dielectric interface (what inspection requirements?) How to sputter seed layer? Interconnect reliability? Inspection for broken metal traces etc. Singulat
